Power-saving clock control apparatus and method
First Claim
1. A clock control type information processing apparatus including a central processing unit for executing programs and at least one peripheral processing unit connected to the central processing unit using a bus comprising:
- a clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the central processing unit and the peripheral processing unit;
a bus access monitoring unit for monitoring load state of the bus which connects the central processing unit with the peripheral processing unit; and
a clock selection control unit for generating control signals to control the clock frequencies generated by the clock generating unit according to the load state of the bus such that one of at least a first, second, and third clock frequency is generated according to a corresponding first, second, and third load state of the bus.
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Abstract
A clock control type information processing apparatus of the invention selects clock frequency according to load state, which reduces electric power consumption without substantially reducing the effective performance of the program. The clock control type information processing apparatus including a central processing unit for executing programs and a plurality of peripheral processing units connected to the central processing unit using a bus, includes a clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the central processing unit and the peripheral processing units, a bus access monitoring unit for monitoring load state of the bus which connects the central processing unit with the peripheral processing units; and a clock selection control unit for generating control signals to control the clock frequencies generated by the clock generating unit according to the load state of the bus.
115 Citations
17 Claims
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1. A clock control type information processing apparatus including a central processing unit for executing programs and at least one peripheral processing unit connected to the central processing unit using a bus comprising:
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a clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the central processing unit and the peripheral processing unit; a bus access monitoring unit for monitoring load state of the bus which connects the central processing unit with the peripheral processing unit; and a clock selection control unit for generating control signals to control the clock frequencies generated by the clock generating unit according to the load state of the bus such that one of at least a first, second, and third clock frequency is generated according to a corresponding first, second, and third load state of the bus. - View Dependent Claims (2, 3, 4)
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5. A clock control type information processing apparatus including a central processing unit for executing the programs and at least one peripheral processing unit connected to the central processing unit using a bus comprising:
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a first clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the peripheral processing unit; a second clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the central processing unit; a bus access monitoring unit for monitoring the load state of the bus which connects the central processing unit with the peripheral processing unit; a first clock selection control unit for generating control signals to switch clock frequencies of the first clock generating unit according to a load state of the bus; and a second clock selection control unit for generating control signals to switch clock frequencies of the second clock generating unit according to a load state of the central processing unit. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A method of controlling a clock and information processing apparatus having a central processing unit and at least one peripheral processing unit operatively connected to the central processing unit with a bus, comprising:
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generating a clock signal having a variable frequency; supplying the clock signal to the central processing unit and the peripheral processing unit; monitoring a load state of the bus; and controlling said generating step to vary the clock signal frequency according to the load state of the bus as determined by said monitoring step such that one of at least a first, second, and third clock frequency is generated according to a corresponding first, second, and third load state of the bus. - View Dependent Claims (13)
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14. A method of controlling clock signals in an information processing apparatus having a central processing unit and a peripheral processing unit operatively connected to the central processing unit via a bus, comprising:
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generating a first clock signal having a variable frequency; supplying the first clock signal to the peripheral processing unit; generating a second clock signal having a variable frequency; supplying the second clock signals to the central processing unit; monitoring a load state of the bus; controlling said generating first clock signal step to vary the first clock signal frequency according to the load state of the bus as determined by said monitoring step; and controlling said generating second clock signal step to vary the frequency of the second clock signal according to a load state of the central processing unit. - View Dependent Claims (15, 16, 17)
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Specification