3-D CMOS-on-SOI ESD structure and method

• US 6,074,899 A
• Filed: 02/05/1999
• Issued: 06/13/2000
• Est. Priority Date: 04/04/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven Howard
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US09/245,488
• Time in Patent Office: 494 Days
• Field of Search: 257/355, 438/155, 438/149, 438/151, 438/153, 438/154
• US Class Current: 438/155
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

Claims

1. A method of making a three-dimensional (3-D) CMOS-on SOI (Complementary-Metal-Oxide-Semiconductor o Silicon-on-Insulator) electrostatic discharge (ESD) structure, said method comprising the steps of:

providing an SOI substrate including a silicon thin film separated from a bulk silicon substrate by an insulator;

forming an ESD network in said bulk silicon substrate;

forming an integrated circuit structure in the thin film of said SOI substrate above said ESD networks; and

connecting said ESD network to a semiconductor chip input pin.

2. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 1, wherein

forming the integrated circuit structure includes forming a MOSFET (metal oxide semiconductor field effect transistor) structure.

3. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 1, wherein

forming the ESD network in the bulk silicon substrate includes forming a bulk portion of a three-dimensional (3-D) ESD network, and

forming the integrated circuit structure includes forming an SOI portion of the 3-D ESD network.

4. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 3, wherein

the SOI portion is a second stage of the 3-D ESD network.

5. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 1, wherein

forming the ESD network includes forming a bulk double diode in a bulk buried well resistor, and

forming the integrated circuit structure includes forming an SOI grounded gate MOSFET positioned over the bulk double diode.

6. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 1, wherein

forming the ESD network includes forming a bulk punch through device, and

forming the integrated circuit structure includes forming an SOI grounded gate MOSFET positioned over the bulk punch through device.

7. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 1, wherein

forming the ESD network includes forming a bulk pnpn silicon controlled rectifier, and

forming the integrated circuit structure includes forming an SOI MOSFET ESD network positioned over the bulk pnpn SCR.

8. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 1, wherein

forming the ESD network includes forming a first bulk ESD network, and

forming the integrated circuit structure includes forming an SOI MOSFET ESD network positioned over the first bulk ESD network, the first bulk ESD network for modulating a surface potential of a bottom surface of the SOI MOSFET ESD network.

9. The method of making a 3-D CMOS-on-SOI ESD structure according to claim 1, wherein

forming the ESD network includes forming a bulk p+ implant in a bulk floating well, and

forming the integrated circuit structure includes forming an SOI p-type MOSFET (PFET) positioned over the ESD network and interconnected to the bulk floating well using a sidewall contact, the SOI PFET for use as a control circuit of the ESD network.