Apparatus and method for forming controlled deep trench top isolation layers

• US 6,074,909 A
• Filed: 07/31/1998
• Issued: 06/13/2000
• Est. Priority Date: 07/31/1998
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Siemens AG
• Inventors: Gruening, Ulrike
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/127,262
• Time in Patent Office: 683 Days
• Field of Search: 438/238, 438/248, 438/282, 438/400, 438/404, 438/243, 438/242, 438/244, 438/424, 438/427, 438/430, 438/270, 438/386, 438/391, 257/301, 257/302, 257/304
• US Class Current: 438/242
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A method for controlling isolation layer thickness in deep trenches for semiconductor memories in accordance with the present invention includes the steps of providing a deep trench having a storage node formed therein, the storage node having a buried strap, depositing an isolation layer on the buried strap for providing electrical isolation for the storage node, forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap and removing the isolation layer except the portion masked by the mask layer such that control of a thickness of the isolation layer is improved. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

Claims

1. A method for controlling isolation layer thickness in trenches for semiconductor memories comprising the steps of:

providing a deep trench having a storage node formed therein, the storage node having a buried strap;

depositing an isolation layer on the buried strap for providing electrical isolation for the storage node;

forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap; and

removing the isolation layer other than the portion masked by the mask layer.

2. The method as recited in claim 1, wherein the step of depositing the isolation layer includes depositing the isolation layer by chemical vapor deposition.

3. The method as recited in claim 1, wherein the step of depositing the isolation layer includes depositing the isolation layer by plasma enhanced chemical vapor deposition.

4. The method as recited in claim 1, wherein the isolation layer includes an oxide.

5. The method as recited in claim 1, wherein the isolation layer includes a nitride.

6. The method as recited in claim 1, wherein the thickness of the isolation layer is between about 20 nm to about 50 nm.

7. The method as recited in claim 1, wherein the step of forming the masking layer includes the step of depositing a material which is selectively etchable relative to the isolation layer.

8. The method as recited in claim 7, wherein the material includes polysilicon.

9. A method for fabricating a memory cell having trench isolation comprising the steps of:

providing a deep trench having a storage node formed therein, the storage node having a buried strap;

depositing an isolation layer on the buried strap for providing electrical isolation for the storage node;

forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap;

selectively etching the isolation layer relative to the masking layer to leave the portion masked by the masking layer;

opening up an isolation trench in communication with the deep trench by removing at least a portion of the substrate adjacent to the deep trench;

filling the isolation trench with a dielectric material to provide trench isolation.

10. The method as recited in claim 9, further comprises the step of forming an access device for accessing the storage node disposed within the deep trench below the isolation layer.

11. The method as recited in claim 10, wherein the step of forming an access device includes forming a transistor having a channel formed in the substrate for electrically coupling the buried strap to a bitline.

12. The method as recited in claim 11, further comprises the step of recessing the portion of the substrate adjacent to the deep trench such that the transistor is formed a greater distance away from the trench.

13. The method as recited in claim 9, further comprises the step of forming a transistor gate adjacent to the trench isolation and adjacent to the isolation layer in a top portion of the deep trench.

14. The method as recited in claim 9, wherein the step of depositing the isolation layer includes depositing the isolation layer by chemical vapor deposition.

15. The method as recited in claim 9, wherein the isolation layer includes an oxide.

16. The method as recited in claim 9, wherein the isolation layer includes a nitride.

17. The method as recited in claim 9, wherein the thickness of the isolation layer is between about 20 nm to about 50 nm.

18. The method as recited in claim 9, wherein the masking layer includes polysilicon.

19. The method as recited in claim 9, wherein the trench isolation includes shallow trench isolation.

20. The method as recited in claim 9, wherein the trench isolation includes raised shallow trench isolation.

21. A method for fabricating a vertical transistor comprising the steps of:

providing a substrate having trenches formed therein, each trench having a storage node formed therein, the storage node having a buried strap;

forming an isolation layer on the buried strap;

laterally etching the substrate to form a recess into the substrate such that the recess extends beyond sides of the trench, the recess being in communication with the trench; and

forming a gate conductor in the recess such that a channel is formed adjacent to the gate conductor for providing electrical conduction between the buried strap and a conductive line upon activation of the gate conductor.

22. The method as recited in claim 21, wherein the step of laterally etching includes laterally etching by a dry etch process.

23. The method as recited in claim 21, wherein the step of laterally etching includes laterally etching by one of a chemical downstream etch and a reactive ion etch process.

24. The method as recited in claim 21, wherein the conductive line includes a bitline.

25. A method for fabricating a vertical transistor for semiconductor memories with deep trenches comprising the steps of:

providing a substrate having deep trenches formed therein, each deep trench having a storage node formed therein, the storage node having a buried strap recessed below a top surface of the substrate;

forming an isolation layer on the buried strap and on trench sidewalls;

depositing a dummy layer on the isolation layer;

opening up an isolation trench in communication with the deep trench by removing at least a portion of the substrate adjacent to the deep trench;

filling the isolation trench with a dielectric material to provide trench isolation;

selectively etching the dummy layer relative to the dielectric material and the isolation layer;

removing the isolation layer from the trench sidewalls; and

forming a vertical transistor adjacent to the portion of the substrate that was removed.