Integration method for sidewall split gate flash transistor

• US 6,074,914 A
• Filed: 10/30/1998
• Issued: 06/13/2000
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Halo Lsi Design & Device Technology, Inc.
• Original Assignee: Halo Lsi Design & Device Technology, Inc.
• Inventors: Ogura, Seiki
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ROCCHEGIANI, RENZO
• Application Number:
  US09/182,777
• Time in Patent Office: 592 Days
• Field of Search: 438/257, 438/593
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor

Abstract

A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

Claims

1. A method of fabricating an electrically programmable read only memory device which is a control/word gate and a floating gate on the side wall of the control/word gate comprising:

providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer;

etching said silicon nitride layer to the dimension of said control/word gate;

forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said floating gate is to be formed;

vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask;

removing said block out mask;

forming an insulator layer on said vertical sidewall;

forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer, wherein the width of said spacer layer is a channel for said device;

ion implanting a N type dopant into said substrate to form a device region therein;

removing said disposable sidewall spacer layer; and

forming a floating gate sidewall spacer on said vertical sidewall and over said channel.

2. The method of claim 1 wherein said channel is planar.

3. The method of claim 1 wherein said channel is non-planar and further comprising:

vertically etching into said substrate after said forming a disposable side wall spacer layer and before said ion implanting to form said non-planar channel.

4. The method of claim 1 wherein said disposable sidewall spacer is composed of polysilicon.

5. The method of claim 1 wherein said disposable sidewall spacer is composed of silicon oxynitride.

6. The method of claim 1 wherein said channel length is between about 30 to 60 nm.

7. The method of claim 1 and further comprising:

forming logic devices in non-memory device area and using simultaneous process steps to form both logic and memory elements.

8. The method of claim 1 wherein said conductive polysilicon layer includes a refractory metal silicide over said polysilicon layer and a silicon nitride layer between said metal silicide layer and said polysilicon layer.

9. A method of fabricating an electrically programmable read only memory device which is a control/word gate and a floating gate on the side wall of the control/word gate while also fabricating logic gates associated therewith in a same silicon substrate comprising:

providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer;

etching said silicon nitride layer to the dimension of said control/word gate in a memory cell area and to the dimension of the logic gate in non-memory areas;

forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said floating gate is to be formed;

vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask;

removing said block out mask;

forming a insulator layer on said vertical sidewall;

forming a disposable sidewall spacer layer on said vertical sidewall and over said insulator layer, wherein the width of said spacer layer is a channel for said device;

ion implanting a N type dopant into said substrate to form a device region therein;

removing said disposable sidewall spacer layer;

forming a floating gate sidewall spacer on said vertical sidewall and over said insulator layer, and over the channel;

forming a block out mask over said silicon nitride layer to cover and protect said control/word gate and said floating gate and to allow all other areas to be uncovered;

removing the exposed said silicon oxide layer;

vertically etching said polysilicon layer to said gate silicon oxide layer to form a vertical sidewall on the opposite side of said floating gate in the memory cell area and to form the logic device gates in logic areas while using said silicon nitride layer on said side uncovered as the mask;

removing said block out mask; and

forming lightly doped drain devices by ion implantation and using a sidewall spacer technique into logic areas at said logic gates.

10. The method of claim 9 wherein the sidewall spacer formed by said sidewall spacer technique is composed of the same material and formed at the same time as the protecting insulating layer over said memory device.

11. The method of claim 9 wherein said channel is planar.

12. The method of claim 9 wherein said channel is non-planar and further comprising:

vertically etching into said substrate after said forming a disposable side wall spacer layer and before said ion implanting to form said non-planar channel.

13. The method of claim 9 wherein said disposable sidewall spacer is composed of polysilicon.

14. The method of claim 9 wherein said disposable sidewall spacer is composed of silicon oxynitride.

15. The method of claim 9 wherein said channel length is between about 30 to 60 nm.

16. A method of fabricating an electrically programmable read only memory device which is a control/word gate, a floating gate on the sidewall of the control/word gate, and an ultra short, non-planar channel comprising:

providing a stack of layers on a silicon substrate, which layers include a gate silicon oxide layer, a conductive polysilicon gate layer, a silicon oxide layer and a silicon nitride layer;

etching said silicon nitride layer to the dimension of said control/word gate;

forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said floating gate is to be formed;

vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask;

removing said block out mask;

forming a insulator layer on said vertical sidewall;

forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer, wherein the width of said spacer layer is a channel for said device;

vertically etching into said substrate to form a step within said substrate;

ion implanting a N type dopant into said step within said substrate to form a device region therein within having said non-planar channel;

removing said disposable sidewall spacer layer; and

forming a floating gate sidewall spacer on said vertical sidewall and over said channel.

17. The method of claim 16 wherein said disposable sidewall spacer is composed of polysilicon.

18. The method of claim 16 wherein said disposable sidewall spacer is composed of silicon oxynitride.

19. The method of claim 16 wherein said channel length is between about 30 to 60 nm.

20. The method of claim 16 and further comprising:

forming logic devices in non-memory device area and using simultaneous process steps to form both logic and memory elements.