Ultra high density inverter using a stacked transistor arrangement

• US 6,075,268 A
• Filed: 11/10/1998
• Issued: 06/13/2000
• Est. Priority Date: 11/07/1996
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kadosh, Daniel, Gardner, Mark I.
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/188,972
• Time in Patent Office: 581 Days
• Field of Search: 257/278, 257/413, 257/369, 257/686, 257/67, 257/69, 257/266, 257/365, 257/758, 257/350, 257/351, 438/152, 438/154, 438/157, 438/283, 438/327
• US Class Current: 257/327
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds the to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows formation of a high density inverter circuit hereof.

Claims

1. An integrated circuit comprising:

a first transistor having a first source implant, a first drain implant and a first gate conductor arranged upon a first topography;

a first interlevel dielectric extending over said first topography, said first interlevel dielectric having an opening which exposes the first gate conductor;

a second transistor having a second source implant, a second drain implant and a second gate conductor which extends over said first interlevel dielectric, wherein said second gate conductor extends below said second source and drain implants and into said opening in electrical abutment with said first gate conductor;

an output conductor abutting an outermost lateral edge of said second drain implant and extending from said outermost lateral edge to an upper surface of said first drain implant;

a power conductor spaced substantially parallel to said output conductor and abutting an upper surface of said second source implant; and

a ground conductor spaced substantially parallel to said output conductor and said power conductor and abutting an upper surface of said first source implant .

2. The integrated circuit as recited in claim 1, wherein said integrated circuit comprises an inverter.

3. The integrated circuit as recited in claim 2, wherein said output conductor, said power conductor and said ground conductor are connected between said first and second transistors to form an inverter.

4. The integrated circuit as recited in claim 2, wherein said output conductor, said power conductor and said ground conductor each extend along an axis perpendicular to said first topography.

5. The integrated circuit as recited in claim 1, wherein said second transistor is inverted relative to said first transistor.

6. The integrated circuit as recited in claim 1, further comprising a silicide interposed between said first gate conductor and said second gate conductor.

7. The integrated circuit as recited in claim 1, wherein said second drain and source implants are doped with an impurity opposite said first drain and source implants.

8. The integrated circuit as recited in claim 1, wherein said second gate conductor completely fills said opening, such that an entire upper surface of the second gate conductor is substantially even with an upper surface of said first interlevel dielectric.

9. An inverter circuit, comprising:

a first transistor having a first gate conductor, a first source implant and a first drain implant, wherein said first gate conductor extends along a plane above said first source and drain implants;

a second transistor having a second gate conductor, a second source implant and a second drain implant, wherein said second gate conductor extends along a plane below said second source and drain implants, and wherein said second gate conductor abuts with said first gate conductor;

an output conductor abutting an outermost lateral edge of said second drain implant and extending from said outermost lateral edge to an upper surface of said first drain implant;

a power conductor spaced substantially parallel to said output conductor and abutting an upper surface of said second source implant; and

a ground conductor spaced substantially parallel to said output conductor and said power conductor and abutting an upper surface of said first source implant.

10. The inverter as recited in claim 9, further comprising a silicide interposed between said first gate conductor and said second gate conductor.

11. The inverter as recited in claim 9, wherein said second drain and source implants are doped with an impurity opposite said first drain and source implants.