Ultra high density inverter using a stacked transistor arrangement
First Claim
1. An integrated circuit comprising:
- a first transistor having a first source implant, a first drain implant and a first gate conductor arranged upon a first topography;
a first interlevel dielectric extending over said first topography, said first interlevel dielectric having an opening which exposes the first gate conductor;
a second transistor having a second source implant, a second drain implant and a second gate conductor which extends over said first interlevel dielectric, wherein said second gate conductor extends below said second source and drain implants and into said opening in electrical abutment with said first gate conductor;
an output conductor abutting an outermost lateral edge of said second drain implant and extending from said outermost lateral edge to an upper surface of said first drain implant;
a power conductor spaced substantially parallel to said output conductor and abutting an upper surface of said second source implant; and
a ground conductor spaced substantially parallel to said output conductor and said power conductor and abutting an upper surface of said first source implant .
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Accused Products
Abstract
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds the to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows formation of a high density inverter circuit hereof.
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Citations
11 Claims
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1. An integrated circuit comprising:
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a first transistor having a first source implant, a first drain implant and a first gate conductor arranged upon a first topography; a first interlevel dielectric extending over said first topography, said first interlevel dielectric having an opening which exposes the first gate conductor; a second transistor having a second source implant, a second drain implant and a second gate conductor which extends over said first interlevel dielectric, wherein said second gate conductor extends below said second source and drain implants and into said opening in electrical abutment with said first gate conductor; an output conductor abutting an outermost lateral edge of said second drain implant and extending from said outermost lateral edge to an upper surface of said first drain implant; a power conductor spaced substantially parallel to said output conductor and abutting an upper surface of said second source implant; and a ground conductor spaced substantially parallel to said output conductor and said power conductor and abutting an upper surface of said first source implant . - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An inverter circuit, comprising:
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a first transistor having a first gate conductor, a first source implant and a first drain implant, wherein said first gate conductor extends along a plane above said first source and drain implants; a second transistor having a second gate conductor, a second source implant and a second drain implant, wherein said second gate conductor extends along a plane below said second source and drain implants, and wherein said second gate conductor abuts with said first gate conductor; an output conductor abutting an outermost lateral edge of said second drain implant and extending from said outermost lateral edge to an upper surface of said first drain implant; a power conductor spaced substantially parallel to said output conductor and abutting an upper surface of said second source implant; and a ground conductor spaced substantially parallel to said output conductor and said power conductor and abutting an upper surface of said first source implant. - View Dependent Claims (10, 11)
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Specification