Surface mount die: wafer level chip-scale package and process for making the same

• US 6,075,290 A
• Filed: 02/26/1998
• Issued: 06/13/2000
• Est. Priority Date: 02/26/1998
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kelkar, Nikhil Vishwanath, Schaefer, William Jeffrey, Kao, Pai-Hsiang
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Potter, Roy
• Application Number:
  US09/031,167
• Time in Patent Office: 838 Days
• Field of Search: 257/737, 257/738, 257/778, 257/787
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Disclosed is an IC package. The IC package includes a die having a plurality of conductive pads. A passivation layer is formed over the conductive pads such that the passivation layer has a plurality of passivation vias. Each passivation via is positioned over an associated one of the conductive pads. A resilient protective layer is formed over the passivation layer. The resilient protective layer has a plurality of resilient vias, wherein each resilient via is associated with an associated passivation via. A plurality of under bump pads are in electrical contact with the conductive pads, and each under bump pad is associated with one of the resilient vias. A plurality of contact bumps are formed over the plurality of under bump pads such that each one of the contact bumps is electrically coupled with a selected one of the under bump pads and such that each contact bump is electrically coupled with a selected one of the conductive pads. The resilient protective layer is arranged to absorb stresses introduced at the contact bumps when the IC package is attached to an external substrate; the contact bumps are formed from a material that facilitates absorption of stresses by the resilient protective layer, and the resilient protective layer is further arranged to protect the die. In one preferred embodiment, each under bump pad includes a lip that extends over a portion of the resilient layer. In another preferred embodiment, the contact bumps are formed from a eutectic tin-lead alloy. In another embodiment, a circuit board is disclosed. The circuit board includes a substrate having a plurality of board contacts and the IC package as recited above. In this embodiment, the IC package is attached to the substrate such that each of the contact bumps is coupled with an associated one of the board contacts. In a preferred embodiment, the resilient protective layer of the IC package absorbs stresses introduced at the contact bumps such that an underfill layer is not required between the IC package and the substrate.

Claims

1. An integrated circuit (IC) package comprising:

a die having a plurality of conductive pads;

a passivation layer formed over the conductive pads such that the passivation layer has a plurality of passivation vias, each passivation via being positioned over an associated one of the conductive pads;

a resilient protective layer formed over the passivation layer, the resilient protective layer having a plurality of resilient vias, each resilient via being associated with an associated passivation via;

a plurality of under bump pads that are in electrical contact with the conductive pads, each under bump pad being associated with one of the resilient vias; and

a plurality of contact bumps formed over the plurality of under bump pads such that each one of the contact bumps is electrically coupled with a selected one of the under bump pads and such that each contact bump is electrically coupled with a selected one of the conductive pads,

wherein the resilient protective layer is formed from a material that absorbs stresses introduced at the contact bumps when the integrated circuit package is attached to an external substrate such that an underfill layer is not required between the IC package and the substrate.

2. The IC package recited in claim 1 wherein each under bump pad includes a lip portion that extends over a portion of the resilient protective layer.

3. The IC package recited in claim 1 wherein the resilient protective layer has a modulus of elasticity of less than about 3.0 GPa.

4. The IC package recited in claim 1, wherein the die includes a top surface that is opposite a bottom surface, the IC package further comprising:

a protective coating over the bottom surface of the die for reducing chipping when the IC package is singulated from a wafer.

5. A circuit board comprising:

a substrate having a plurality of board contacts;

the IC package as recited in claim 1 attached to the substrate such that each of the contact bumps is coupled with an associated one of the board contacts.

6. The circuit board as recited in claim 5, wherein the resilient protective layer of the IC package absorbs stresses introduced at the contact bumps such that an underfill layer is not required between the IC package and the substrate.

7. The IC package recited in claim 5, wherein the IC package is a one selected from the group comprising a surface mount package, a chip scale package, and a flip chip type package.

8. The IC package recited in claim 1, wherein the contact bumps are formed from a eutectic tin-lead alloy.

9. The IC package recited in claim 8, wherein the eutectic tin-lead alloy has a composition of about 63 percent tin and about 37 percent lead.

10. The IC package recited in claim 1, wherein the eutectic tin-lead alloy has a composition of at most 40 percent lead.

11. The IC package recited in claim 1, wherein the eutectic tin-lead alloy has a composition of at least 60 percent tin.

12. The IC package recited in claim 1, wherein each under bump pad forms a plurality of steps over portions of the passivation layer and the resilient protective layer.

13. The integrated circuit package recited in claim 1, wherein the IC package has a size that is substantially equal to that of the die.

14. The integrated circuit package recited in claim 1, wherein the contact bumps have a pitch of about 500 μ

m.

15. The IC package recited in claim 1, wherein the vias of the resilient protective layer are formed so as to avoid contact between the resilient protective layer and the conductive pads.

17. The IC package recited in claim 1 wherein the resilient protective layer has a thickness of greater than about 4 μ

m.

18. The IC package recited in claim 1 wherein the resilient protective layer has a thickness of between about 4 and about 10 μ

m.

16. An integrated circuit (IC) package comprising:

a die having a plurality of conductive pads;

a passivation layer formed over the conductive pads such that the passivation layer has a plurality of passivation vias, each passivation via being positioned over a associated one of the conductive pads;

a resilient protective layer formed over the passivation layer, the resilient protective layer having a plurality of resilient vias, each resilient via being associated with an associated passivation via;

a plurality of under bump pads that are in electrical contact with the conductive pads, each under bump pad being associated with one of the resilient vias; and

a plurality of contact bumps formed over the plurality of under bump pads such that each one of the contact bumps is electrically coupled with a selected one of the under bump pads and such that each contact bump is electrically coupled with a selected one of the conductive pads,

wherein the resilient protective layer is one of a group consisting of polyimide and benzocyclobutene (BCB) material.