Method, architecture and circuit for half-rate clock and/or data recovery
First Claim
Patent Images
1. A circuit comprising:
- an oscillator configured to generate a first clock signal and a second clock signal in response to a control signal;
a multiplexer configured to generate said control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal;
a half rate clock circuit configured to generate said half rate clock signal in response to said first and second clock signals; and
a full rate clock circuit configured to generate said full rate clock in response to (i) one of said first and second clock signals and (ii) a reference clock.
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Abstract
A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.
52 Citations
16 Claims
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1. A circuit comprising:
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an oscillator configured to generate a first clock signal and a second clock signal in response to a control signal; a multiplexer configured to generate said control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal; a half rate clock circuit configured to generate said half rate clock signal in response to said first and second clock signals; and a full rate clock circuit configured to generate said full rate clock in response to (i) one of said first and second clock signals and (ii) a reference clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit comprising:
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means for generating a first clock signal and a second clock signal in response to a control signal; means for generating said control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal; means for generating said half rate clock signal in response to said first and second clock signals; and means for generating said full rate clock in response to (i) one of said first and second clock signals and (ii) a reference clock.
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12. A method for data recovery comprising the steps of:
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(A) generating a first clock signal and a second clock signal in response to a control signal; (B) generating said control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal; (C) generating said half rate clock signal in response to said first and second clock signals; and (D) generating said full rate clock in response to (i) one of said first and second clock signals and (ii) a reference clock. - View Dependent Claims (13, 14, 15, 16)
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Specification