Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips

• US 6,075,710 A
• Filed: 02/11/1999
• Issued: 06/13/2000
• Est. Priority Date: 02/11/1998
• Status: Expired due to Fees

• Current Assignee: Express Imaging Systems, LLC
• Original Assignee: Express Imaging Systems, LLC
• Inventors: Lau, John H.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): FOSTER, DAVID A
• Application Number:
  US09/248,875
• Time in Patent Office: 488 Days
• Field of Search: 361/760, 361/764, 361/765, 361/767, 361/772, 257/737, 257/738, 257/778, 257/780, 228/180.21, 228/180.22, 174/250, 174/254, 174/255, 174/260, 174/261, 174/266
• US Class Current: 361/760
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 2201/10719 : Land grid array [LGA]
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3485 : Applying solder paste, slurry or powder thick film methods for applying conductive paste or ink patterns H05K3/12
• CPC Class Codes: H05K 3/363 : by soldering
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

The present invention discloses a novel electronic package. This semiconductor packaging assembly is for supporting and containing an integrated circuit (IC) chip. The IC chip is supported on a single core double-layer substrate as a flip chip which is solder-bumped with low melting point solder, e.g., a 63 wt % Sn-37 wt % Pb eutectic solder. The flip chip is supported on a single core double-sided FR-4/5 or BT substrate provided with via holes to form via connections interconnecting the solder bumps to a land grid array disposed on the bottom surface of the substrate. The substrate is then surface mounted and soldered onto a printed circuit board which again is provided with low temperature 63 wt % Sn-37 wt % Pb eutectic solder paste for securely attaching the LGA CSP. Simplified processes are employed to assemble the electronic package with high yield processing steps, which can be conveniently carried out. CSP package with high reliability and improved performance characteristics can be achieved with a reduced production cost. This invention further discloses a tape-substrate provided for interposing between a semiconductor chip and a printed circuit board (PCB). The tape substrate includes a bottom insulation layer. The tape substrate further includes a plurality of conductive pads disposed on top of the bottom insulation layer for electrical connection to the semiconductor chip. The tape substrate further includes a plurality of PCB contact-openings opened in the insulation layer and a plurality of PCB contact-pads, each covering one of the PCB contact-openings for electrical connection to circuit on the PCB. The tape substrate further includes a plurality of connection means for interconnecting the conductive pads to the PCB contact-pads.

Claims

1. A chip scale electronic package assembly provided for supporting an integrated circuit (IC) chip disposed as a flip-chip having a plurality of solder bumps for external electric connection therefrom, said package assembly comprising:

a tape substrate having a patterned conductive layer includes a plurality of solder-bump contact pads each having a corresponding solder paste contact pad interconnected with a conductive trace wherein each of said contact pads disposed at a location corresponding to one of said solder bumps, and each of said solder paste contact pads disposed at a location corresponding to one of said solder pastes;

said tape substrate further includes a top insulation layer having a plurality of solder-bump contact openings opened on top of each of said solder-bump contact pads;

said tape substrate further includes a bottom insulation layer having a plurality of solder-paste contact openings open right below the solder-paste contact pads;

said IC chip mounted on said tape substrate having each of said solder-bumps electrically contacting a corresponding solder bump contact-pad.

2. The package assembly of claim 1 further comprising:

a printed circuit board having a plurality of copper-pads with solder paste disposed thereon wherein said tape substrate mounted onto said printed circuit board with each of said copper-pads with solder paste disposed in said solder-paste contact-openings for soldering to and electrically connected to a corresponding solder-paste contact-pad.

3. The package assembly of claim 2 wherein:

said solder bumps on said flip-chip and said solder pastes on said PCB composed of a low-melting soldering material.

4. The package assembly of claim 3 wherein:

said low-melting soldering material is a 63 wt % Sn-37 wt % Pb eutectic solder.

5. The package assembly of claim 1 wherein:

said tape-substrate having a thickness ranging between one to four mils.

6. A tape-substrate provided for interposing between a flip-chip with a plurality of solder bumps and a printed circuit board (PCB) with a plurality of PCB copper-pads with solder paste provided for electrically connecting to a one of said solder bumps, comprising:

a patterned conductive layer includes a plurality of solder-bump contact pads each having a corresponding solder paste contact pad interconnected with a conductive trace wherein each of said contact pads disposed at a location corresponding to one of said solder bumps, and each of said solder paste contact pads disposed at a location corresponding to one of said solder pastes;

a top insulation layer having a plurality of solder-bump contact openings opened on top of each of said solder-bump contact pads; and

a bottom insulation layer having a plurality of solder-paste contact openings open right below the solder-paste contact pads.

7. The tape-substrate of claim 6 wherein:

said tape-substrate having a thickness ranging between one to four mils.

8. The tape-substrate of claim 6 wherein:

said patterned conductive layer with said solder bump contact pads, said solder paste contact pads, and said conductive traces composed of copper.

9. The tape-substrate of claim 6 further comprising:

a top adhesive layer for attaching said top insulation layer to said patterned conductive layer and a bottom adhesive layer for attaching said bottom insulation layer to said patterned conductive layer.

10. The tape-substrate of claim 6 wherein:

said top insulation layer and said bottom insulation layer composed of polyimide.

11. A tape-substrate provided for interposing between a semiconductor chip and a printed circuit board (PCB), comprising:

a patterned conductive layer includes a plurality of solder-bump contact pads each having a corresponding solder paste contact pad interconnected with a conductive trace;

a top insulation layer having a plurality of solder-bump contact openings opened on top of each of said solder-bump contact pads; and

a bottom insulation layer having a plurality of solder-paste contact openings open right below the solder-paste contact pads.

12. A method for manufacturing a tape-substrate for interposing between a semiconductor chip and a printed circuit board (PCB), comprising steps of:

patterning a conductive layer covered by a top insulation layer to form a plurality of solder-bump contact pads and a plurality of corresponding solder-paste contact pads and patterning a plurality of conductive traces for interconnecting each of solder-bump contact pads to one of said corresponding solder paste contact pads;

opening a plurality of solder-bump contact openings in said top insulation layer on top of and exposing each of said solder-bump contact pads;

attaching a bottom insulation layer below said patterned conductive layer; and

opening a plurality of solder-paste contact openings in said bottom insulation layer right below and exposing each of said solder-paste contact pads.

13. A method for interposing a tape-substrate between a flip-chip with a plurality of solder bumps and a printed circuit board (PCB) with a plurality of PCB copper-pads with solder paste provided for electrically connecting to a one of said solder bumps, comprising:

patterning a conductive layer to form a plurality of solder-bump contact pads at locations corresponding to said solder bumps;

patterning said conductive layer to form a plurality of solder-paste contact pads at locations corresponding to said solder pastes;

patterning a plurality of conductive traces for interconnecting each of said solder-bump contact pads to a corresponding solder paste contact pads;

covering said conductive layer with a top insulation layer and opening a plurality of solder-bump contact openings on top of each of said solder-bump contact pads;

covering said conductive layer with a bottom insulation layer and opening a plurality of solder-paste contact openings right below said solder-paste contact pads; and

mounting said IC chip onto said tape substrate with each of said solder-bumps contacting and soldering to said solder-bump contact pads.

14. The method of claim 13 further comprising a step of:

mounting said tape substrate onto said printed circuit board (PCB) with each of said solder-pastes contacting and soldering to said solder-paste contact pads.