Flip-chip having electrical contact pads on the backside of the chip

• US 6,075,712 A
• Filed: 01/08/1999
• Issued: 06/13/2000
• Est. Priority Date: 01/08/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McMahon, John F.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US09/227,650
• Time in Patent Office: 522 Days
• Field of Search: 361/767, 361/768, 361/792-795, 361/783, 257/684, 257/690, 257/698, 257/700, 257/701, 257/702, 257/723, 257/724, 257/735, 257/737, 257/738, 257/773, 257/774, 257/775, 257/777, 257/778, 257/780, 257/784, 438/108, 438/125, 438/928, 333/185, 174/255, 174/256, 174/258
• US Class Current: 361/783
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/91 Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite the first surface. Circuit elements are formed within the first surface. A plurality of bump contacts are located on the first surface and connected to the circuit elements. Bond pads that are also connected to circuit elements are located within or on the second surface.

Claims

1. An integrated circuit device comprising:

a semiconductor substrate having a first surface and a second surface opposite said first surface;

circuit elements disposed within said first surface;

a conductor region over said first surface having a top-side surface;

a first plurality of electrical contact pads disposed on said top-side surface and connected to said circuit elements through said conductor region;

a second plurality of electrical contact pads disposed within said second surface and connected to said circuit elements; and

conductor power traces for power input, at least one of said second plurality of electrical contact pads connected to said power traces.

2. The integrated circuit device of claim 1 wherein said second plurality of electrical contact pads are adaptable for establishing a wire bond connection.

3. The integrated circuit device of claim 1 wherein said second plurality of electrical contact pads bond pads are adaptable for establishing a TAB bond connection.

4. The integrated circuit device of claim 1 wherein said conductor region further comprises conductor lines electrically connecting said circuit elements, at least one of said second plurality of electrical contact pads coupled to at least one of said conductor lines.

5. The integrated circuit device of claim 1 wherein said conductor region further comprises a first layer and a second layer of conductor lines electrically connecting said circuit elements, said first layer of conductor lines located adjacent to said circuit elements, at least one of said second plurality of electrical contact pads coupled to at least one of said first layer conductor lines.

6. The integrated circuit device of claim 1 wherein said second plurality of electrical contact pads are disposed within recesses in said second surface of said semiconductor substrate.

7. The integrated circuit device of claim 6 wherein said second plurality of electrical contact pads comprise a metal layer deposited within said recesses.

8. The integrated circuit device of claim 7 further comprising an insulation layer disposed over said metal layer.

9. The integrated circuit device of claim 1 further comprising solder bumps connected to said first plurality of electrical contact pads.

10. The integrated circuit device of claim 1 further comprising a memory device located on said integrated circuit device and electrically coupled to at least one of said second plurality of electrical contact pads.

11. An integrated circuit device comprising:

a semiconductor substrate having a first surface and a second surface opposite said first surface;

at least one recess in said second surface;

circuit elements disposed within said first surface;

a conductor region above said first surface comprising conductor lines electrically connecting said circuit elements, said conductor region having a top-side surface;

a first plurality of contact pads disposed on said top-side surface and connected to said circuit elements; and

,

a second plurality of contact pads disposed within said at least one recess and connected to contacts external to said substrate.

12. The integrated circuit device of claim 11 wherein said second contact pads comprise a metal layer disposed within said recess.

13. The integrated circuit device of claim 12 further comprising an insulation layer disposed over said metal layer.

14. The integrated circuit device of claim 11 wherein said second contact pads are adaptable for establishing a wire bond connection.

15. The integrated circuit device of claim 11 wherein said second contact pads are adaptable for establishing a TAB bond connection.

16. An apparatus comprising:

a semiconductor substrate having a first surface and a second surface opposite said first surface;

circuit elements disposed within said first surface;

a conductor region located over said first surface having a top-side surface;

a first plurality of contact pads disposed on said top-side surface and connected to said circuit elements through said conductor region;

a second plurality of contact pads disposed within said second surface and connected to said circuit elements; and

,

a printed circuit board having a first set of bond pads and a second set of bond pads, said first plurality of contact pads being electrically coupled to said first set of bond pads and said second plurality of contact pads being electrically coupled to said second set of bond pads.

17. The apparatus of claim 16 wherein at least one of said second plurality of contact pads is electrically coupled to said second set of bond pads by a wire bond.

18. The apparatus of claim 16 wherein said second plurality of contact pads is electrically coupled to said second set of bond pads by a TAB bond.

19. The apparatus of claim 16 wherein said first plurality of contact pads is coupled to said first set of bond pads by solder connections.

20. The apparatus of claim 16 wherein said second plurality of electrical contact pads are disposed within recesses in said second surface of said semiconductor substrate.

21. The apparatus of claim 20 wherein said second plurality of contact pads comprise a metal layer deposited within said recesses.

22. The apparatus of claim 21 further comprising an insulation layer disposed over said metal layer.