Method for sorting semiconductor devices having a plurality of non-volatile memory cells

• US 6,075,724 A
• Filed: 02/22/1999
• Issued: 06/13/2000
• Est. Priority Date: 02/22/1999
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Vantiss (Lattice Semiconductor Corporation)
• Inventors: Mehta, Sunil D., Li, Xiao-Yu
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/255,410
• Time in Patent Office: 477 Days
• Field of Search: 365/185.18, 365/185.09, 365/185.02, 365/201
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A method for sorting semiconductor devices having a plurality of non-volatile memory cells effectively screens memory cells with a predicted lifetime less than a desired lifetime, in part, by determining a minimum acceptable voltage value and a maximum acceptable voltage drop value for each cell in the device at a margin sort read point. In the method of the invention, the device is first stressed by programming and erasing the memory cells for a predetermined number of cycles. After stressing the device, the device is erased and an initial voltage across a floating-gate is measured at time=0. The initial voltage value is compared with acceptable minimum and maximum initial voltages. The device is discarded if the initial voltage value is outside of the range defined by the minimum and maximum initial voltages. Next, the device is baked at a predetermined temperature. Then, a voltage drop value is determined by measuring a second voltage on the floating-gate at the margin sort read point. The device is identified as defective and discarded if both the second voltage value of any cell is below the predetermined minimum value, and if the voltage drop value of the cell exceeds a predetermined maximum voltage drop value.

Claims

1. A method for sorting a semiconductor device having a plurality of non-volatile memory cells each including a floating-gate transistor comprising the steps of:

alternatingly programming and erasing the device to provide a stressed device;

erasing the stressed device;

measuring a first voltage across the floating-gate of each memory cell to determine an initial voltage value;

baking the device at a predetermined temperature;

measuring a second voltage across the floating-gate of each memory cell, and subtracting the second voltage from the first voltage to determine a voltage drop value; and

discarding the device if the second voltage value of any cell is below a predetermined minimum value and if the voltage drop value of the cell exceeds a predetermined maximum voltage drop value.

2. The method of claim 1 further comprising the step of storing the device at a predetermined temperature and for a predetermined time prior to baking the device.

3. The method of claim 2, wherein the step of storing the device comprises storing the device at room temperature, and wherein the step of baking the device comprises baking the device at a temperature above about 200°

C.

4. The method of claim 1, wherein the step of baking the device comprises baking the device at a temperature above about 250°

C.

5. A method for sorting a semiconductor device having a plurality of non-volatile memory cells each including a floating-gate transistor comprising the steps of:

alternatingly programming and erasing the device to provide a stressed device;

erasing the stressed device;

measuring a first voltage across the floating-gate of each memory cell to determine an initial voltage value;

storing the device for a predetermined period of time at a first temperature;

baking the device at a second temperature;

measuring a second voltage across the floating-gate of each memory cell;

subtracting the first voltage from the second voltage to determine a voltage drop value for each cell; and

discarding the device only if;

     1) the second voltage value of any cell is below a predetermined minimum initial value; and

     2) the voltage drop value of the cell exceeds a predetermined maximum voltage drop value.

6. The method of claim 5, wherein the step of storing the device at a first temperature comprises storing the device at room temperature, and wherein the step of baking the device at a second temperature comprises baking the device at a temperature above about 200°

C.

7. The method of claim 5, wherein the step of measuring a second voltage across the floating-gate of each memory cell comprises measuring the second voltage at a predetermined time period after measuring the first voltage.

8. The method of claim 7, wherein the step of measuring a second voltage across the floating-gate of each memory cell comprises measuring the second voltage about 24 to 72 hours after measuring the first voltage.

9. A method for sorting a non-volatile memory device having a plurality of memory cells each including a floating-gate transistor comprising the steps of:

specifying predicted voltage decay characteristics for normal memory cells to determine an end of life target value;

defining a margin sort read point;

specifying a minimum initial voltage value and a maximum voltage drop value at the margin sort read point based on the predicted voltage decay characteristics of normal memory cells;

measuring a first voltage across the floating-gate of each memory cell to determine an initial voltage value;

measuring a second voltage across the floating-gate of each memory cell at the margin sort read point;

determining a voltage drop value from the first and second voltages; and

discarding the device if;

     1) the second N voltage value of any cell is below the minimum initial value, and

     2) the voltage drop value of the cell exceeds the maximum voltage drop value.

10. The method of claim 9, wherein the step of measuring a first voltage across the floating-gate of each memory cell to determine an initial voltage value further comprises the steps of:

determining acceptable minimum and maximum initial voltage values;

comparing the initial voltage value with the acceptable minimum and maximum initial voltage values; and

discarding the device if the initial voltage value is not within a range defined by the minimum and maximum initial voltage values.

11. The method of claim 9, wherein the step of specifying a minimum voltage value and a maximum voltage drop value comprises setting the initial voltage value at about 1.5 volts and setting the maximum voltage drop value at about 0.5 volts.

12. The method of claim 9 further comprising the steps of alternatingly programming and erasing the device to provide a stressed device and erasing the stressed device prior to the step of measuring the first voltage.

13. The method of claim 9 further comprising the step of baking the device at a predetermined temperature prior to the step of measuring the second voltage.

14. The method of claim 13, wherein the step of baking the device comprises baking the device at a temperature of no less than about 250°

C.

15. The method of claim 13, wherein the step of defining a margin sort read point comprises defining the margin sort read point after the step of baking the device.

16. The method of claim 13 further comprising the step of storing the device at a predetermined temperature and for a predetermined time prior to baking the device.

17. The method of claim 16, wherein the step of storing the device comprises storing the device at room temperature.

18. The method of claim 9, wherein the step of defining a margin sort read point comprises defining the margin sort read point at about 24 to 72 hours after measuring the first voltage.

19. The method of claim 9, wherein the step of specifying predicted voltage decay characteristics for normal memory cells to determine an end of life target value comprises determining an end of life at about 10 years after the step of measuring a first voltage.

20. The method of claim 9, wherein the step of determining a voltage drop value from the first and second voltages comprises measuring the first and second voltages across a tunnel oxide layer having a thickness of less than about 100 angstroms and subtracting the first voltage from the second voltage to determine a voltage drop value for each cell.