DRAM device with function of producing wordline drive signal based on stored charge in capacitor

• US 6,075,746 A
• Filed: 02/26/1998
• Issued: 06/13/2000
• Est. Priority Date: 02/28/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohsawa, Takashi
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/030,945
• Time in Patent Office: 838 Days
• Field of Search: 365/230.06, 365/189.09, 365/202, 365/189.11
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A DRAM device includes plural cell arrays two-dimensionally arranged in column and row directions. A wordline driving section has a drive transistor in each row for transferring a charge to a corresponding cell in the plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method. A first generating section generates a drive signal for driving a wordline which is supplied to the drive transistor, based on a stored charge in a capacitor. A second generating section generates a control signal for controlling the gate of the drive transistor in a chip of the DRAM device by a charge pump circuit.

Claims

1. A semiconductor device comprising:

plural cell arrays two-dimensionally arranged in column and row directions;

a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in said plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method;

a first generating section for generating a drive signal for driving a wordline which is supplied to said drive transistor, the drive signal being generated based on a stored charge in a capacitor; and

a second generating section for generating a control signal for controlling the gate of said drive transistor in a chip of the DRAM device by a charge pump circuit.

5. The semiconductor device according to claim 1, wherein the charge pump circuit comprises two or more charge pump circuits connected in series.

9. The semiconductor device according to claim 1, wherein the wordline driving section is operated in such a manner that in a test mode where said wordlines are driven in a multiplicity, the same number of wordlines as that in an ordinary operation is driven in a first cycle and other wordlines are driven in a second cycle without resetting the wordlines already driven in the first cycle.

11. The semiconductor device according to claim 1, wherein said semiconductor device comprises plural banks each of which a decode control can be independently applied to and each bank being provided with the first generating section.

16. An LSI according to claim 1, wherein the LSI comprises the semiconductor device and a LSI with a logic function, said semiconductor and the LSI being fabricated in the same chip.

17. The semiconductor device according to claim 1, wherein said drive transistor in at least the last row is PMOS, the drive signal generated by said first generating section is supplied to a source of the PMOS and the control signal generated by said second generating section is supplied to other circuits.

25. The semiconductor device according to claim 1, wherein a circuit of said first generating section comprises:

first and second inverters connected in series with each other to which an original signal is input;

a capacitor; and

a CMOS inverter which comprises

a first transistor a source of which is connected to a power supply;

a second transistor; and

a third transistor, said first, second and third transistors being connected to one another in cascade connection,

wherein the original signal is input to a gate of said first transistor, a first end of said capacitor is connected to said first inverter, a second end of said capacitor is connected to a drain of said first transistor and a source of said second transistor, said second inverter is connected to a common gate between said second and third transistors, and a drive signal for driving said wordline is output from a common drain between said second and third transistors.

2. A semiconductor device comprising:

plural cell arrays two-dimensionally arranged in column and row directions;

a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in said plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method;

a bitline equalization signal driving section in which a bitline equalization signal is generated by raising a voltage;

a first generating section for generating the bitline equalization signal based on a stored charge in a capacitor; and

a second generating section for generating a control signal for controlling the gate of said drive transistor in a chip of the DRAM device by a charge pump circuit.

6. The semiconductor device according to claim 2, wherein the charge pump circuit device comprises two or more charge pump circuits connected in series.

12. The semiconductor device according to claim 2, wherein said semiconductor device comprises plural banks each of which a decode control can be independently applied to and each bank being provided with the first generating section.

18. The semiconductor device according to claim 2, wherein said drive transistor in at least the last row is PMOS, the drive signal generated by said first generating section is supplied to a source of the PMOS and the control signal generated by said second generating section is supplied to other circuits.

26. The semiconductor device according to claim 2, wherein a circuit of said first generating section comprises:

a first inverter to which an original signal is input;

a NAND circuit to which the original signal is input;

a first transistor having a source connected to a power supply, and a gate to which the original signal is input;

a capacitor;

second and third transistors having sources connected to each other and a gate of one transistor being connected to a drain of the other transistor;

a fourth transistor having a drain connected to a drain of said second transistor;

a fifth transistor having a drain connected to a drain of said third transistor; and

a CMOS inverter comprising sixth and seventh transistors connected to each other in cascade connection;

wherein a first end of said capacitor is connected to said first inverter and a second end of said capacitor is connected to a drain of said first transistor and sources of said second, third and sixth transistors, said NAND circuit is connected to a gate of said fourth transistor and a gate of said fifth transistor through a second inverter, common drain between said third and fifth transistors is connected to a common gate between said sixth and seventh transistors, and a bitline equalization signal is output from a common drain between said sixth and seventh transistors.

28. The semiconductor device according to claim 26, wherein a row block select signal for selecting one row block among plural row blocks is input to said NAND circuit, said row block select signal being generated based on a combination of plural row addresses.

3. A semiconductor device comprising:

plural cell arrays two-dimensionally arranged in column and row directions;

a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in said plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method;

a bitline separation signal driving section for transferring a charge between a bitline and a sense amplifier by raising a voltage of a bitline separation signal;

a first generating section for generating the bitline separation signal based on a stored charge in a capacitor; and

a second generating section for generating a control signal for controlling the gate of said drive transistor by a charge pump circuit.

7. The semiconductor according to claim 3, wherein the charge pump circuit comprises two or more charge pump circuits connected in series.

13. The semiconductor device according to claim 3, wherein said semiconductor device comprises plural banks each of which a decode control can be independently applied to and each bank being provided with the first generating section.

19. The semiconductor device according to claim 3, wherein said drive transistor in at least the last row is PMOS, the drive signal generated by said first generating section is supplied to the source of the PMOS and the control signal generated by said second generating section is supplied to other circuits.

27. The semiconductor device according to claim 3, wherein a circuit of said first generating section comprises:

a first inverter to which an original signal is input;

a NAND circuit to which the original signal is input;

a first transistor having a source connected to a power supply;

a capacitor;

second and third transistors having sources connected to each other and a gate of one transistor being connected to a drain of the other transistor;

a fourth transistor having a drain connected to a drain of said second transistor;

a fifth transistor having a drain connected to a drain of said third transistor;

a second inverter connected to said fourth and fifth transistors; and

a CMOS inverter comprising sixth and seventh transistors connected to each other in cascade connection;

wherein a first end of said capacitor is connected to said first inverter, a second end of said capacitor is connected to a drain of said first transistor and sources of said second, third and sixth transistors, said NAND circuit is connected to a gate of said fourth transistor, a common drain between said third and fifth transistors is connected to a common gate between said sixth and seventh transistors, and a bitline separation signal is output from a common drain between said sixth and seventh transistors.

29. The semiconductor device according to claim 27, wherein a row block select signal for selecting one row block among plural row blocks is input to said NAND circuit, said row block select signal being generated based on a combination of plural row addresses.

4. A semiconductor device comprising:

plural cell arrays two-dimensionally arranged in column and row directions;

a wordline driving section having a drive transistor in each row for transferring a charge to a corresponding cell in said plural cell arrays by raising a voltage on a wordline selected by a plural stage decode method;

a bitline equalization signal driving section for effecting equalization by raising a voltage of a bitline equalization signal;

a bitline separation signal driving section for transferring a charge between a bitline and a sense amplifier by raising a voltage of a bitline separation signal;

a first generating section for generating a drive signal for driving a wordline which is supplied to said drive transistor, said drive signal being generated based on a stored charge in a capacitor;

a second generating section for generating the bitline equalization signal based on a stored charge in a capacitor;

a third generating section for generating the bitline separation signal based on a stored charge in a capacitor; and

a fourth generating section for generating a control signal for controlling the gate of said drive transistor by a charge pump circuit.

8. The semiconductor device according to claim 4, wherein the charge pump circuit comprises two or more charge pump circuits connected in series.

10. The semiconductor device according to claim 4, wherein the wordline driving section is operated in such a manner that in a test mode where said wordlines are driven in a multiplicity, the same number of wordlines as that in an ordinary operation is driven in a first cycle and the rest of the wordlines are driven in a second cycle without resetting the wordlines already driven in the first cycle.

14. The semiconductor device according to claim 4, wherein said semiconductor device comprises plural banks each of which a decode control can be independently applied to and each bank being provided with the first generating section.

15. The semiconductor device according to claim 4, wherein said semiconductor device comprises:

one or plural banks which or each of which can be independently decoded; and

said first generating section or the same number of first generating sections as that of said plural banks, wherein the wordline drive signal, the bitline equalization signal and the bitline separation signal are supplied to the one or each bank by decode using an address for allocation to each bank in the case of said plural banks.

20. The semiconductor device according to claim 4, wherein said drive transistor in at least the last row is PMOS, the drive signal generated by the first generating section is supplied to the source of the PMOS and the control signal generated by the second generating section is supplied to other circuits.

21. A semiconductor device comprising:

plural cell arrays two-dimensionally disposed in row and column directions;

a sense amplifier region, which is disposed at a boundary in a column direction of said plural cell arrays, and which is separated by a transistor to a gate of which a bitline separation signal is input and commonly used;

a driver region for a wordline disposed at a boundary in a row direction of said plural cell arrays on both edges of a row decoder as a center;

a driving circuit for driving the bitline separation signal and a bitline equalization signal disposed in a crossing region of said sense amplifier region and said row decoder region;

a first generating section for generating at least one selected from the group consisting of a drive signal for driving said wordline, the bitline separation signal and the bitline equalization signal based on a stored charge in a capacitor; and

a second generating section for generating a control signal for controlling a gate of a drive transistor in said driver region by a charge pump circuit.

22. The semiconductor device according to claim 21, wherein said charge pump circuit is disposed almost in the center of a semiconductor chip, on which the semiconductor device is formed.

23. The semiconductor device according to claim 21, wherein plural charge pump circuits are disposed along upper and lower directions from the center of the chip.

24. The semiconductor device according to claim 21, wherein said row decoder is commonly used by the wordline driver region disposed on both edges of the row decoder.