Video-image histogram equalization circuit and method therefor

• US 6,075,890 A
• Filed: 06/25/1997
• Issued: 06/13/2000
• Est. Priority Date: 06/27/1996
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Se-woong
• Primary Examiner(s): Tran, Phuoc
• Application Number:
  US08/882,261
• Time in Patent Office: 1,084 Days
• Field of Search: 382/168, 382/169, 348/671, 348/672, 348/673, 348/670, 358/522, 358/445, 358/447, 358/521, 358/443
• US Class Current: 382/169
• CPC Class Codes: G06T 5/40 using histogram techniques
• CPC Class Codes: G06T 5/92 based on global image properties

Abstract

A histogram equalization circuit includes a calculator and a mapper. The calculator calculates cumulative distribution function (CDF) values for the respective gray levels with respect to an input image corresponding to an area signal of a predetermined period. The mapper maps the input image of a predetermined period to a new gray level based on the CDF values of the respective gray levels. The present invention obtains a CDF value by selecting a field period or a frame period as a CDF calculation area and performs a histogram equalization the image signal of the selected period based on the CDF value. Calculation of the CDF is performed by direct comparison of the pixels of the image, thus eliminating the need to calculate a probability density function for the gray levels. Therefore, it is possible to obtain a high correlation between the input data and the equalized data and to reduce the quantity of hardware.

Claims

1. A histogram equalization circuit for enhancing contrast by controlling gray level dynamic range with respect to an input image signal expressed by a predetermined number of gray levels, said histogram equalization circuit comprising:

calculation means for calculating cumulative distribution function (CDF) values for the respective gray levels with respect to the input image signal, corresponding to an area signal of a predetermined period, by counting the number of pixels having values which are not more than the respective gray levels and dividing the counted result by the total number of samples in the input image; and

mapping means for mapping the input image signal to a new gray level based on the CDF values of said respective gray levels;

wherein said calculation means comprises;

a plurality of comparators for comparing the values of the input image signal with the respective gray levels;

a plurality of accumulators for accumulating the respective outputs of said plurality of comparators according to said area signal and outputting the number of pixels which have values not more than the respective gray levels; and

a plurality of dividers for dividing the respective outputs of said plurality of accumulators by the total number of samples with respect to said input image of the predetermined period and outputting the divided results as CDF values of the respective gray levels.

2. The histogram equalization circuit as claimed in claim 1, wherein said area signal of the predetermined period is the CDF calculation area of a frame period.

3. The histogram equalization circuit as claimed in claim 2, wherein said input image signal of the predetermined period is the frame image.

4. The histogram equalization circuit as claimed in claim 1, wherein said area signal of the predetermined period is the CDF calculation area of a field period.

5. The histogram equalization circuit as claimed in claim 4, wherein said input image of the predetermined period is the frame image.

6. A histogram equalization circuit for enhancing contrast by controlling gray level dynamic range with respect to an input image signal expressed by a predetermined number of gray levels, said histogram equalization circuit comprising:

calculation means for calculating cumulative distribution function (CDF) values for the respective gray levels with respect to the input image signal, corresponding to an area signal of a predetermined period, by counting the number of pixels having values which are not more than the respective gray levels and dividing the counted result by the total number of samples in the input image;

mapping means for mapping the input image signal to a new gray level based on the CDF values of said respective gray levels; and

a field memory for delaying said input image signal by one field;

wherein said calculation means comprises;

a plurality of comparators for comparing the values of the input image signal with the respective gray levels;

a plurality of accumulators for accumulating the respective outputs of said plurality of comparators according to said area signal and outputting the number of pixels having values not more than the respective gray levels; and

a plurality of dividers for dividing the respective outputs of said plurality of accumulators by the total number of samples of said input image of said predetermined period and outputting the divided results as CDF values of the respective gray levels.

7. The histogram equalization circuit as claimed in claim 6, wherein said area signal of the predetermined period is the CDF calculation area of a field period.

8. The histogram equalization circuit as claimed in claim 7, wherein said input image signal of the predetermined period is the field image.

9. A histogram equalization circuit for enhancing contrast by controlling gray level dynamic range with respect to an input image signal expressed by a predetermined number of gray levels, said histogram equalization circuit comprising:

calculation means for calculating cumulative distribution function (CDF) values for the respective gray levels with respect to the input image signal, corresponding to an area signal of a predetermined period, by counting the number of pixels having values which are not more than the respective gray levels and dividing the counted result by the total number of samples in the input image;

mapping means for mapping the input image signal to a new gray level based on the CDF values of said respective gray levels; and

a field memory for delaying said input image signal by one field;

wherein said calculation means comprises;

selecting means for selecting one of the input image signal corresponding to an odd field and the input image signal corresponding to an even field according to a field synchronizing signal;

first comparing means comprised of a plurality of comparators for comparing the values of the input image signal corresponding to the odd field selected by said selecting means with the respective gray levels;

second comparing means comprised of a plurality of comparators for comparing the values of the input image signal corresponding to the even field selected by said selecting means with the respective gray levels;

first accumulating means comprised of a plurality of accumulators for accumulating the output of said first comparing means according to a first area signal and outputting the number of pixels having values not ore than the respective gray levels;

second accumulating means comprised of a plurality of accumulators for accumulating the output of said second comparing means according to a second area signal and outputting the number of pixels having values not more than the respective gray levels;

adding means comprised of a plurality of adders for adding the outputs of the respective accumulators of said first accumulating means to the outputs of the respective accumulators of said second accumulating means, respectively;

latching means comprised of a plurality of latches for latching the respective outputs of said plurality of adders and outputting the latched signal according to said field synchronizing signal; and

dividing means comprised of a plurality of dividers for dividing the respective outputs of said plurality of latches by the total number of samples of the input image of the predetermined period and outputting the divided results as CDF values of the respective gray levels.

10. The histogram equalization circuit as claimed in claim 9, wherein said first area signal represents the CDF calculation area of the odd field period and said second area signal represents the CDF calculation area of the even field period.

11. The histogram equalization circuit as claimed in claim 10, wherein said calculation means outputs the CDF value obtained by adding the CDF value of an (m-1)th field to the CDF value of an mth field, said mapping means maps the image signal of said mth field to a new level based on said added CDF value, and m is a predetermined number.

12. A histogram equalization method for enhancing contrast by controlling a gray level with respect to an input image signal expressed by a predetermined number of gray levels, comprising the steps of:

(a) calculating cumulative distribution function (CDF) values for the respective gray levels by counting the number of pixels in the image signal having values which are not more than the respective gray levels and dividing the counted result by the total number of samples with respect to the input image corresponding to an area signal of a predetermined period; and

(b) mapping the input image signal of a predetermined period to a new gray level based on the CDF values of the respective gray levels;

wherein said area signal of the predetermined period is the CDF calculation area of a field period; and

wherein in said step (a), the CDF value obtained by adding the CDF value of an (m-1)th field to the CDF value of an mth field is output, and m is a predetermined number.

13. The histogram equalization method as claimed in claim 12, wherein in said step (b), the image signal of said mth field is mapped to a new gray level based on the added CDF value.