Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction

• US 6,075,929 A
• Filed: 06/05/1996
• Issued: 06/13/2000
• Est. Priority Date: 06/05/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: MacLaren, John M.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/658,496
• Time in Patent Office: 1,469 Days
• Field of Search: 395/309, 395/310, 395/311, 395/306, 395/473, 395/474, 395/494, 395/464, 395/465, 395/250, 395/872, 395/873, 395/876, 395/298, 395/305, 395/287, 395/292, 395/853, 395/854 , 395/859, 395/877, 395/881
• US Class Current: 710/311
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 13/4054 where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus

Abstract

A computer system includes a memory device on the first data bus, a requesting device that initiates a delayed memory read transaction on a second data bus, and a bridge device that delivers the delayed memory read transaction to the first data bus and receives from the first data bus completion data requested in the memory read transaction. The bridge device includes a data storage buffer that stores the completion data, and a buffer management element that automatically requests from the memory device additional data to be placed in the data storage buffer.

Claims

1. A computer system comprising:

a memory device on a first data bus,

a requesting device that places, on a second data bus, an initial read transaction directed to the memory device and that relinquishes control of the second data bus while awaiting a response to the initial read transaction, and

a bridge device that operatively connects the first and second data buses and that, in response to the initial read transaction, places a subsequent read transaction on the first data bus and receives from the first data bus, data responsive to the initial read transaction, comprising;

a data storage buffer that stores the data responsive to the initial read transaction, and

a buffer management element that automatically requests from the memory device additional data beyond the data responsive to the initial read transaction.

2. The computer system of claim 1 wherein the buffer management element requests additional data only after the requesting device has retrieved all of the data from the data storage buffer.

3. The computer system of claim 1 wherein the additional data is located at a location that follows sequentially a location at which the requested data is stored in the memory device.

4. The computer system of claim 1 wherein the requesting device requests a predetermined amount of data.

5. The computer system of claim 4 wherein the buffer management element automatically requests the predetermined amount of additional data.

6. The computer system of claim 1 wherein the requesting device requests an entire cache line of data.

7. The computer system of claim 1 wherein the requesting device requests multiple cache lines of data.

8. The computer system of claim 1 wherein if the requesting device removes all of the additional data from the buffer, the buffer management element again automatically requests additional data from the memory device.

9. The computer system of claim 1 further comprising a prediction element that allows the buffer management element to selectively retrieve additional data.

10. The computer system of claim 9 wherein the prediction element prevents the buffer management element from again automatically requesting additional data if the requesting device fails to remove all data from the storage buffer.

11. The computer system of claim 9 wherein the prediction element allows the buffer management element to automatically request additional data when the requesting device removes all data from the data storage buffer.

12. The computer system of claim 1 wherein the second bus comprises a PCI bus.

13. The computer system of claim 1 wherein the bridge device comprises a PCI-to-PCI bridge.

14. The computer system of claim 1 wherein the initial read transaction comprises a memory read line transaction.

15. The computer system of claim 1 wherein the initial read transaction comprises a memory read multiple transaction.

26. The computer system of claim 1 wherein the buffer management element is configured to request additional data automatically only after the requesting device has retrieved all of the data from the data storage buffer and has indicated that it wants additional data.

27. The computer system of claim 26 wherein the buffer management element is configured to request additional data automatically only when the requesting device has indicated that it wants data from a location that follows sequentially a location at which the requested data is stored in the memory device.

16. A computer system comprising:

a memory device on a first PCI bus,

a PCI device that initiates a delayed memory read transaction on a second PCI bus, and

a PCI-to-PCI bridge operatively connecting the first and second PCI buses and comprising;

a delayed completion buffer that stores a predetermined amount of data from the memory device requested in the delayed memory read transaction, and

a buffer management element that automatically requests from the memory device the predetermined amount of additional data after the PCI device removes all of the data from the delayed completion buffer.

17. The computer system of claim 16 wherein the buffer management element again initiates a request for the predetermined amount of additional data when the PCI device removes all of the additional data from the storage buffer.

18. In a computer system having a memory device on a first data bus and a requesting device that places, on a second data bus, an initial read transaction directed to the memory device and that relinquishes control of the second data bus while awaiting a response to the initial read transaction, a method for use in a component operatively connecting the first and second data buses, the method comprising:

in response to the initial read transaction, placing, on the first data bus, a subsequent read transaction,

storing in a data storage buffer data received from the first data bus that is responsive to the initial read transaction, and

automatically requesting from the memory device additional data beyond the data responsive to the initial read transaction.

19. The method of claim 18 wherein the additional data is requested only if the requesting device retrieves all of the data from the data storage buffer.

20. The method of claim 18 wherein the initial read transaction requests a predetermined amount of data.

21. The method of claim 18 wherein the amount of additional data retrieved equals the predetermined amount.

22. The method claim 18 wherein the predetermined amount of data comprises eight cache lines.

23. The method of claim 18 further comprising disabling future automatic retrieval of additional data if the requesting device fails to retrieve all of the data stored in the data storage buffer.

24. The method of claim 18 wherein the initiating bus comprises a PCI bus.

25. The method of claim 18 wherein the first and second data buses are connected by a PCI-to-PCI bridge.

28. The computer system of claim 18 further comprising automatically requesting additional data only if the requesting device retrieves all of the data from the data storage buffer and indicates that it wants additional data.

29. The computer system of claim 28 further comprising automatically requesting the additional data only if the requesting device indicates that it wants data from a location that follows sequentially a location at which the requested data is stored in the memory device.

30. The method of claim 18 further comprising again automatically requesting additional data from the memory device if the requesting device removes all of the additional data from the buffer.

35. The computer system of claim 30 wherein the prediction element prevents the bridge device from again requesting additional data if the requesting device fails to remove all data from the buffer.

36. The computer system of claim 30 wherein the prediction element allows the bridge device to request additional data when the requesting device removes all data from the buffer.

31. A computer system comprising:

a memory device on a first data bus,

a requesting device that places, on a second data bus, an initial read transaction directed to the memory device and that relinquishes the second data bus while awaiting a response to the initial read transaction, and

a bridge device that operatively connects the first and second data buses and that;

in response to the initial read transaction, places a subsequent read transaction on the first data bus,

stores, in a buffer, data that is received from the memory device and that is responsive to the initial read transaction, and

automatically requests from the memory device additional data beyone the data responsive to the initial read transaction.

32. A computer system comprising:

a memory device on a first data bus,

a requesting device that places on a second data bus a read transaction directed to the memory device and that relinquishes control of the second data bus while awaiting a response to the read transaction, and

a bridge device that operatively connects the first and second data buses and that;

stores, in a buffer, data that is received from the memory device and that is responsive to the read transaction,

automatically requests from the memory device additional data beyond the data responsive to the intitial read transaction, and

if the requesting device retrieves all of the additional data, again automatically requests additional data from the memory device.

33. In a computer system having a memory device on a first data bus and a requesting device that places on a second data bus a read transaction directed to the memory device and then relinquishes control of the second data bus while awaiting a response to the read transaction, a method for use in a component operatively connecting the first and second data buses, the method comprising:

storing, in a buffer, data that is received from the memory device and that is responsive to the read transaction,

automatically requesting from the memory device additional data beyond the data responsive to the initial read transaction, and

if the requesting device retrieves all of the additional data, again automatically requesting additional data from the memory device.

34. A computer system comprising:

a memory device on a first data bus,

a requesting device that places on a second data bus a read transaction directed to the memory device and that relinquishes control of the second data bus while awaiting a response to the read transaction,

a bridge device that operatively connects the first and second data buses and that;

stores, in a buffer, data that is received from the memory device and that is responsive to the read transaction, and

includes a prediction element that allows the bridge device to request from the memory device, selectively and automatically, additional data beyond the data responsive to the read transaction.