Method and apparatus to force a thread switch in a multithreaded processor
First Claim
1. A method of computer processing, comprising:
- (a) setting a first time-out value;
(b) loading a decrementer register when a thread switch occurs to a first thread;
(c) executing the first thread of instructions in a multithreaded processor;
(d) decrementing the decrementer register every time period the first thread executes until the decrementer register reaches a first limit;
(e) sending a first time-out signal to a thread switch controller when the first limit is equivalent to the first time-out value and the first thread of instructions is not performing useful processing.
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Accused Products
Abstract
A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.
309 Citations
17 Claims
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1. A method of computer processing, comprising:
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(a) setting a first time-out value; (b) loading a decrementer register when a thread switch occurs to a first thread; (c) executing the first thread of instructions in a multithreaded processor; (d) decrementing the decrementer register every time period the first thread executes until the decrementer register reaches a first limit; (e) sending a first time-out signal to a thread switch controller when the first limit is equivalent to the first time-out value and the first thread of instructions is not performing useful processing. - View Dependent Claims (2, 3, 4)
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5. A method of computer processing, comprising:
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(a) setting a first time-out value; (b) loading a decrementer register when a thread switch occurs to a first thread; (c) executing the first thread of instructions in a multithreaded processor; (d) decrementing the decrementer register every period the first thread executes until the decrementer register reaches a first limit; (e) sending a first time-out signal to a thread switch controller when the first limit is equivalent to the first time-out value (f) setting a second time-out value different from the first time-out value; (g) loading the decrementer register when a thread switch occurs to a second thread; (h) decrementing the decrementer every time period the second thread executes until the decrementer register reaches a second limit; (i) sending a second time-out signal to the thread switch controller when the second limit is equivalent to the second time-out value.
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6. A method of computer processing, comprising:
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(a) loading a decrementer register when a thread switch occurs to a first thread; (b) setting a first time-out value less than five times longer than a most frequent longest latency event which inhibits the first thread from executing; (c) executing the first thread of instructions in a multithreaded processor; (d) decrementing the decrementer register every period the first thread executes until the decrementer register reaches a first limit; (e) sending a first time-out signal to a thread switch controller when the first limit is equivalent to the first time-out value. - View Dependent Claims (7)
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8. A computer processor, comprising:
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(a) a multithreaded processor capable of switching between at least two threads of instructions, at least one of the threads being an active thread executing instructions in the multithreaded processor; (b) a time-out counter which counts the number of cycles that the active thread executes; and (c) a time-out register operatively connected to the multithreaded processor and having a predetermined number which generates a time-out signal when the time-out counter equals the predetermined number in the time-out register and the active thread is unable to perform useful processing of instructions. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A computer system, comprising:
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(a) a multithreaded processor capable of switching processing between at least two threads of instructions when the multithreaded processor experiences one of a plurality of processor latency events; (b) a plurality of internal connections connecting the multithreaded processor to a plurality of memory elements wherein access to any of the plurality of memory elements by the multithreaded processor causes one of the plurality of processor latency events; (c) a plurality of external connections connecting the multithreaded processor to at least one external memory device, at least one external communication device, an external computer network, or at least one input/output device wherein access to any of the devices or the network by the multithreaded processor causes one of the plurality of processor latency events (d) at least one time-out counter which counts the number of cycles that each of the at least two threads of instructions executes; (e) at least one time-out register operatively connected to the multithreaded processor and having a predetermined number which generates a time-out signal when the at least one time-out counter equals the predetermined number in the at least one time-out register; (f) a thread switch controller which sends a switch signal to said multithreaded processor in response to the time-out signal and forces the multithreaded processor to switch to another of the at least two threads.
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15. A computer processor, comprising:
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(a) means for processing a thread of instructions; (b) means for switching said thread of instructions into or out of said processing means; (c) means for counting a number of cycles that said processing means is processing; (d) means for storing a time-out value; and (e) means for generating a time-out signal when said number of cycles is equal to said time-out value and said thread of instructions is not performing useful processing when said thread is in said processing means. - View Dependent Claims (16, 17)
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Specification