Verification system for simulator

• US 6,077,304 A
• Filed: 09/14/1998
• Issued: 06/20/2000
• Est. Priority Date: 04/15/1996
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Kasuya, Atsushi
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/152,956
• Time in Patent Office: 645 Days
• Field of Search: 395/500.35, 395/500.38, 395/680, 395/183.07, 395/183.13, 395/500.06, 703/14, 709/300
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.

Claims

1. A computer program product for use in conjunction with a computer system, the computer program product configured to direct the computer system to verify operation of a specified system, the computer program product comprising a computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism comprising:

verification procedures for interconnection with a set of simulation procedures so as to interleave performance of system verification operations with system simulation operations;

the verification procedures including instructions for executing a test bench so as to define operational correctness and/or performance criteria for the specified system, the operational correctness and/or performance criteria including an Expect Event, the Expect Event comprising a combination of one or more signal values that are expected to occur during simulation of the specified system, and a time frame during which the signal value combination is expected to occur;

wherein the time frame for the Expect Event has a specified simulation start time and a specified nonzero, finite duration; and

the verification procedures including instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation of the specified system and the time frame expiring.

2. The computer program product of claim 1,

the Expect Event having an associated failure action to be performed if the signal value combination fails to occur during the time frame;

and

the verification procedures including instructions for determining, upon receiving control from the simulation procedures, whether the Expect Event has failed and for then performing the associated failure action.

3. The computer program product of claim 2,

the verification procedures specifying to the simulation procedures a list of watched signals whose values are specified in the Expect Event;

and

the simulation procedures including a simulation engine for simulating operation of the specified system in accordance with specified input signal waveforms until any signal included in the watched signal list specified by the verification procedures changes value, and for then passing control to the verification procedures.

4. The computer program product of claim 1,

the verification procedures including instructions for performing a success action when the Expect Event has been satisfied;

and

a subset of the success actions including executing instructions that affect operation of the simulation procedures.

5. The computer program product of claim 1,

the verification procedures including instructions for performing a respective success action when a respective one of the Expect Events has been satisfied, and instructions for performing a respective failure action when the signal value combination for the respective one of the Expect Events fails to occur during the time frame;

and

a subset of the success and failure actions including executing instructions that affect operation of the simulation procedures.

6. The computer program product of claim 5, a subset of the success and failure actions including executing instructions for sending input signal waveforms to the simulation procedures for use while simulating operation of the specified system.

7. The computer program product of claim 1,

the operational correctness and/or performance criteria including a Full Expect Event, the Full Expect Event comprising a combination of one or more signal values that are expected to remain true for an associated time frame during simulation of the specified system;

wherein the time frame for the Full Expect Event has a specified simulation start time and a specified nonzero, finite duration; and

the verification procedures including instructions for performing a failure action if the signal value combination for the Full Expect Event fails to remain true during the Full Expect Event'"'"'s associated time frame.

8. The computer program product of claim 1,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

and

the verification procedures including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs, the combination of events comprising a combination of event signals generated by various ones of the threads during execution of the threads.

9. The computer program product of claim 1,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

and

the verification procedures including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs, the combination of events comprising a combination of event signals generated in a specified order by various ones of the threads during execution of the threads.

10. The computer program product of claim 1,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

the verification procedures including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs;

the verification procedures including instructions for creating and executing child threads in response to execution of a predefined fork command by a parent thread comprising one of the multiple threads, and for blocking the parent thread'"'"'s execution after execution of the fork command;

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of all of the child threads.

11. The computer program product of claim 1,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

the verification procedures including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs;

the verification procedures including instructions for creating and executing child threads in response to execution of a predefined fork command by a parent thread comprising one of the multiple threads, and for blocking the parent thread'"'"'s execution after execution of the fork command;

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of any of the child threads.

12. The computer program product of claim 1,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

the verification procedures including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs; and

the verification procedures including instructions for responding to execution of resource request commands by respective ones of the threads by blocking execution of each respective thread for which a predefined resource request command has been executed until all resources in a list of resources specified by the predefined resource request command are available, and for then marking as unavailable the resources in the list of resources.

13. A simulation and verification system, comprising:

a simulator and verifier coupled so as to pass control back and forth between each other;

the verifier executing a test bench so as to define operational correctness and/or performance criteria for a specified system, the operational correctness and/or performance criteria including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation of the specified system, and a time frame during which the signal value combination is expected to occur;

wherein the time frame for each Expect Event has a specified simulation start time and a specified nonzero, finite duration; and

the verifier including instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation of the specified system and the time frame expiring.

14. The simulation and verification system of claim 13,

the Expect Event having an associated failure action to be performed if the signal value combination fails to occur during the time frame;

and

the verifier including instructions, upon receiving control from the verifier, for determining whether the Expect Event has failed and for then performing the associated failure action.

15. The simulation and verification system of claim 14,

the verifier specifying to the simulator a list of watched signals that includes signals whose values are specified in the at least one Expect Event;

and

the simulator including a simulation engine for simulating operation of a specified system in accordance with specified input signal waveforms until any signal including in the watched signal list specified by sad verifier changes value, and for then passing control to the verifier.

16. The simulation and verification system of claim 13,

the verifier including instructions for performing a respective success action when a respective one of the Expect Events has been satisfied;

and

a subset of the success actions including executing instructions that affect operation of the simulator.

17. The simulation and verification system of claim 13,

the verifier including instructions for performing a respective success action when a respective one of the Expect Events has been satisfied, and instructions for performing a respective failure action when the signal value combination fails for the respective one of the Expect Events to occur during the time frame;

and

a subset of the success and failure actions including executing instructions that affect operation of the simulator.

18. The simulation and verification system of claim 17, at least a subset of the success and failure actions including executing instructions for sending input signal waveforms to the simulator for use while simulating operation of the specified system.

19. The simulation and verification system of claim 13,

the operational correctness and/or performance criteria including at least one Full Expect Event, each Full Expect Event comprising a combination of one or more signal values that are expected to remain true for an associated time frame during simulation of the specified system;

wherein the time frame for each Full Expect Event has a specified simulation start time and a specified nonzero, finite duration; and

the verifier including instructions for performing a failure action if the signal value combination for a respective Full Expect Event fails to remain true during the respective Full Expect Event'"'"'s associated time frame.

20. The simulation and verification system of claim 13,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

and

the verifier including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs, the combination of events comprising a combination of event signals generated by various ones of the threads during execution of the threads.

21. The simulation and verification system of claim 13,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

and

the verifier including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs, the combination of events comprising a combination of event signals generated in a specified order by various ones of the threads during execution of the threads.

22. The simulation and verification system of claim 13,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

the verifier including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs;

the verifier including instructions for creating and executing child threads in response to execution of a predefined fork command by a parent thread comprising one of the multiple threads, and for blocking the parent thread'"'"'s execution after execution of the fork command;

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of all of the child threads.

23. The simulation and verification system of claim 13,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

the verifier including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs;

the verifier including instructions for creating and executing child threads in response to execution of a predefined fork command by a parent thread comprising one of the multiple threads, and for blocking the parent thread'"'"'s execution after execution of the fork command;

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of any of the child threads.

24. The simulation and verification system of claim 13,

the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled;

the verifier including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs; and

the verifier including instructions for responding to execution of resource request commands by respective ones of the threads by blocking execution of each respective thread for which a predefined resource request command has been executed until all resources in a list of resources specified by the predefined resource request command are available, and for then marking as unavailable the resources in the list of resources.

25. A computer program product for use in conjunction with a computer system, the computer program product configured to direct the computer system to verify operation of a specified system, the computer program product comprising a computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism comprising:

verification procedures for interconnection with a set of simulation procedures so as to interleave performance of verification operations with simulation operations;

the verification procedures including instructions for executing a test bench so as to define operational correctness and/or performance criteria for the specified system, the operational correctness and/or performance criteria including at least one Full Expect Event, each Full Expect Event comprising a combination of one or more signal values that are expected to remain true for an associated time frame during simulation of the specified system;

wherein the time frame for each Full Expect Event has a specified simulation start time and a specified nonzero, finite duration; and

the verification procedures including instructions for performing a failure action if the signal value combination for a respective Full Expect Event fails to remain true during the respective Full Expect Event'"'"'s associated time frame.

26. A simulation and verification system, comprising:

a simulator and verifier coupled so as to pass control back and forth between each other;

the verifier executing a test bench so as to define operational correctness and/or performance criteria for a specified system, the operational correctness and/or performance criteria including at least one Full Expect Event, each Full Expect Event comprising a combination of one or more signal values that are expected to remain true for an associated time frame during simulation of the specified system;

wherein the time frame for each Full Expect Event has a specified simulation start time and a specified nonzero, finite duration; and

the verifier including instructions for performing a failure action if the signal value combination for a respective Full Expect Event fails to remain true during the respective Full Expect Event'"'"'s associated time frame.

27. A computer program product for use in conjunction with a computer system, the computer program product configured to direct the computer system to verify operation of a specified system, the computer program product comprising a computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism comprising:

verification procedures for interconnection with a set of simulation procedures so as to interleave performance of verification operations with simulation operations;

the verification procedures including instructions for executing a test bench so as to define operational correctness and/or performance criteria for the specified system, the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled; and

the verification procedures further including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs.

28. The computer program product of claim 27,

wherein the combination of events comprises a combination of event signals generated by various ones of the threads during execution of the threads.

29. The computer program product of claim 27,

the verification procedures including instructions for creating and executing child threads in response to execution of a predefined fork command by a parent thread comprising one of the multiple threads, and for blocking the parent thread'"'"'s execution after execution of the fork command;

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of all of the child threads.

30. The computer program product of claim 27,

the verification procedures including instructions for creating and executing child threads of execution in response to execution of a predefined fork command by a parent thread comprising one of the multiple threads, and for blocking the parent thread'"'"'s execution after execution of the fork command;

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of any of the child threads of execution.

31. The computer program product of claim 27,

the verification procedures including instructions for responding to execution of resource request commands by respective ones of the threads by blocking execution of each respective thread for which a predefined resource request command has been executed until all resources in a list of resources specified by the predefined resource request command are available, and for then marking as unavailable the resources in the list of resources.

32. The computer program product of claim 31,

wherein the resources in the list of resources continue to be marked as unavailable until the respective thread releases the resources in the list of resources or execution of the respective thread is completed.

33. A simulation and verification system, comprising:

a simulator and verifier coupled so as to pass control back and forth between each other;

the verifier executing a test bench so as to define operational correctness and/or performance criteria for the specified system, the test bench including multiple concurrent threads, each thread having associated actions to be performed by the thread when execution of the thread is enabled; and

the verifier further including thread synchronization instructions for blocking execution of respective ones of the threads until, for each blocked thread, a respective defined combination of events occurs;

wherein

the combination of events comprises a combination of event signals generated by various ones of the threads during execution of the threads; and

the verification procedures include instructions for creating and executing child threads in response to execution of a predefined fork command by a parent thread comprising one of the multiple threads, and for blocking the parent thread'"'"'s execution after execution of the fork command.

34. The simulation and verification system of claim 33,

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of all of the child threads.

35. The simulation and verification system of claim 33,

wherein the respective defined combination of events for unblocking the parent thread'"'"'s execution comprises completing execution of any of the child threads of execution.

36. The simulation and verification system of claim 33,

the verifier including instructions for responding to execution of resource request commands by respective ones of the threads by blocking execution of each respective thread for which a predefined resource request command has been executed until all resources in a list of resources specified by the predefined resource request command are available, and for then marking as unavailable the resources in the list of resources.

37. The simulation and verification system of claim 36,

wherein the resources in the list of resources continue to be marked as unavailable until the respective thread releases the resources in the list of resources or execution of the respective thread is completed.