Compiling system and method for partially reconfigurable computing
First Claim
1. A compiling method for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising the steps of:
- a) accepting as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements;
b) identifying a first configuration of the selectively reconfigurable portion of the processing unit to be used in executing the first subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the first configuration;
c) identifying a second configuration of the selectively reconfigurable portion of the processing unit to be used in executing the second subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the second configuration; and
compiling the first subset of instruction statements for execution using the first configuration and compiling the second subset of instruction statements for execution using the second configuration.
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Accused Products
Abstract
A compiling system and method generates a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations. A compiler selectively compiles high-level source code statements for execution using configurations of the reconfigurable portion of the processing unit responsive to meta-syntax compiler directives. A linker creates object files that optionally encapsulate bitstreams specifying hardware organizations corresponding to the configurations.
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Citations
30 Claims
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1. A compiling method for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising the steps of:
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a) accepting as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements; b) identifying a first configuration of the selectively reconfigurable portion of the processing unit to be used in executing the first subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the first configuration; c) identifying a second configuration of the selectively reconfigurable portion of the processing unit to be used in executing the second subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the second configuration; and compiling the first subset of instruction statements for execution using the first configuration and compiling the second subset of instruction statements for execution using the second configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A compiling method for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising:
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a) selecting a source code instruction statement from a source file containing a plurality of source code instruction statements; b) responsive to the statement comprising a function call, performing the steps of; b.1) determining a first configuration currently in context within the selectively reconfigurable portion of the processing unit; b.2) determining a second configuration for the function call; b.3) responsive to the first configuration being different than the second configuration, emitting a reconfiguration statement; b.4) emitting a compiled code statement for the function call; c) responsive to the statement not comprising a function call, emitting a compiled code statement for the statement; and d) repeating a) through c) for each source code instruction statement in the source file. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A compiling system for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising:
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an input device for inputting at least one source file containing a plurality of source code instruction statements, including at least a first subset of instruction statements, a second subset of instruction statements, and, for each subset of instruction statements, a reconfiguration directive specifying a configuration for the selectively reconfigurable portion of the processing unit; and a compiler, coupled to receive each source file from the input device, for compiling each input source file to produce an object file by identifying the configuration corresponding to each reconfiguration directive, compiling at least a portion of the input source file for execution using each configuration, and generating a reconfiguration code corresponding to each reconfiguration directive. - View Dependent Claims (22, 23)
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24. A computer program product comprising a computer-usable medium having computer-readable code embodied therein for generating a sequence of program instructions for use in a partially reconfigurable processing unit, comprising:
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computer-readable program code devices configured to accept as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements; computer-readable program code devices configured to identify a first configuration of the selectively reconfigurable portion of the processing unit to be used in executing the first subset of instruction statements; computer-readable program code devices configured to identify a second configuration of the selectively reconfigurable portion of the processing unit to be used in executing the second subset of instruction statements; and computer-readable program code devices configured to compile the first subset of instruction statements for execution using the first configuration and compiling the second subset of instruction statements for execution using the second configuration. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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Specification