Compiling system and method for partially reconfigurable computing

• US 6,077,315 A
• Filed: 01/09/1998
• Issued: 06/20/2000
• Est. Priority Date: 04/17/1995
• Status: Expired due to Fees

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Greenbaum, Jack E., Baxter, Michael A.
• Primary Examiner(s): Hafiz, Tariq R.
• Application Number:
  US09/005,218
• Time in Patent Office: 893 Days
• Field of Search: 395/709, 717/9
• US Class Current: 717/157
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading

Abstract

A compiling system and method generates a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations. A compiler selectively compiles high-level source code statements for execution using configurations of the reconfigurable portion of the processing unit responsive to meta-syntax compiler directives. A linker creates object files that optionally encapsulate bitstreams specifying hardware organizations corresponding to the configurations.

Claims

1. A compiling method for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising the steps of:

a) accepting as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements;

b) identifying a first configuration of the selectively reconfigurable portion of the processing unit to be used in executing the first subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the first configuration;

c) identifying a second configuration of the selectively reconfigurable portion of the processing unit to be used in executing the second subset of instruction statements, by retrieving a reconfiguration directive from the source file, the reconfiguration directive specifying the second configuration; and

compiling the first subset of instruction statements for execution using the first configuration and compiling the second subset of instruction statements for execution using the second configuration.

2. The method of claim 1, wherein each reconfiguration directive is provided using a meta-syntax.

3. The method of claim 1, wherein each reconfiguration directive comprises one of an immediate reconfiguration directive, a function-level reconfiguration directive, and a default reconfiguration directive.

4. The method of claim 1, further comprising the step of:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a reconfiguration code identifying the configuration corresponding to the subset of instruction statements.

5. The method of claim 1, further comprising the step of:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a reference designating a bitstream representing the hardware configuration to be used in executing the subset of instruction statements.

6. The method of claim 1, further comprising the step of:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a reference encoded according to an extended executable and linking format, the reference designating a bitstream representing the hardware configuration to be used in executing the subset of instruction statements.

7. The method of claim 1, further comprising the step of:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a bitstream representing the hardware configuration to be used in executing the subset of instruction statements.

8. The method of claim 1, further comprising the steps of:

e) generating a first object file including the results of d) and further including, for each subset of instruction statements, a reconfiguration code identifying the hardware configuration to be used in executing the subset of instruction statements;

f) repeating a) through e) for at least a second source file to generate at least a second object file; and

g) linking the object files generated in e) and f) to generate an executable file.

9. The method of claim 8, further comprising the step of:

h) performing memory alignment on the generated executable file according to alignment requirements.

10. The method of claim 9, wherein the generated executable file is associated with a bitstream representing a configuration, and wherein step h) further comprises:

h.1) padding the bitstream to perform memory alignment.

11. The method of claim 8, wherein:

step a) comprises accepting as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements, wherein at least one of the instruction statements contains an external reference; and

step e) comprises generating a first object file including the results of d) and further including, for each subset of instruction statements, a reconfiguration code identifying the hardware configuration to be used in executing the subset of instruction statements, wherein at least one of the instruction statements contains an external reference;

and further comprising the step of;

f.

     1) prior to g), resolving the external references of each object file.

12. The method of claim 1, wherein the first subset of instruction statements comprises a first defined function and the second subset of instruction statements comprises a second defined function.

13. The method of claim 1, wherein the first subset of instruction statements comprises a first arbitrary block of statements and the second subset of instruction statements comprises a second arbitrary block of statements.

14. The method of claim 13, wherein the source file includes at least one function call and function return, and wherein steps b) and c) each comprise selectively performing inter-procedural analysis to identify at each function call and function return an in-context configuration within the selectively reconfigurable portion of the processing unit.

15. A compiling method for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising:

a) selecting a source code instruction statement from a source file containing a plurality of source code instruction statements;

b) responsive to the statement comprising a function call, performing the steps of;

b.1) determining a first configuration currently in context within the selectively reconfigurable portion of the processing unit;

b.2) determining a second configuration for the function call;

b.3) responsive to the first configuration being different than the second configuration, emitting a reconfiguration statement;

b.4) emitting a compiled code statement for the function call;

c) responsive to the statement not comprising a function call, emitting a compiled code statement for the statement; and

d) repeating a) through c) for each source code instruction statement in the source file.

16. The method of claim 15, wherein b.4) comprises:

b.4.1) emitting a compiled code statement for reading a return value from the selectively reconfigurable portion of the processing unit; and

b.4.2) emitting a compiled code statement for the function call.

17. The method of claim 15, wherein the code statements comprise register transfer level statements.

18. The method of claim 17, further comprising:

e) for each register transfer level statement;

e.1) responsive to the register transfer statement being a reconfiguration statement, emitting assembly code for reconfiguring the selectively reconfigurable portion of the processing unit to a configuration specified by the reconfiguration statement;

e.2) responsive to the register transfer level statement not being a reconfiguration statement, determining whether the statement may be executed by the selectively reconfigurable portion of the processing unit using a configuration currently in context;

e.3) responsive to a determination that the statement may be executed by the selectively reconfigurable portion of the processing unit using the in-context configuration, performing the steps of;

e.3.1) emitting assembly code for copying data into the selectively reconfigurable portion of the processing unit;

e.3.2) emitting assembly code for starting execution of the selectively reconfigurable portion of the processing unit; and

e.3.3) emitting assembly code for reading a return value from the selectively reconfigurable portion of the processing unit;

e.4) responsive to a determination that the statement may not be executed by the selectively reconfigurable portion of the processing unit using the in-context configuration, performing the steps of;

e.4.1) determining whether a translation rule exists for the register transfer level statement; and

e.4.2) responsive to a determination that a translation rule exists, emitting assembly code for the register transfer level statement according to the translation rule.

19. The method of claim 18, wherein e.2) comprises the steps of:

e.2.1) creating a first data flow graph describing a register transfer level tree;

e.2.2.) creating a second data flow graph describing the in-context configuration of the selectively reconfigurable portion of the processing unit; and

e.2.1.) determining whether the first data flow graph matches the second data flow graph.

20. The method of claim 18, wherein e.3.2) comprises generating code for setting a counter within the selectively reconfigurable portion of the processing unit to a nonzero value.

21. A compiling system for generating a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations, the compiling method comprising:

an input device for inputting at least one source file containing a plurality of source code instruction statements, including at least a first subset of instruction statements, a second subset of instruction statements, and, for each subset of instruction statements, a reconfiguration directive specifying a configuration for the selectively reconfigurable portion of the processing unit; and

a compiler, coupled to receive each source file from the input device, for compiling each input source file to produce an object file by identifying the configuration corresponding to each reconfiguration directive, compiling at least a portion of the input source file for execution using each configuration, and generating a reconfiguration code corresponding to each reconfiguration directive.

22. The compiling system of claim 21, further comprising:

a linker, coupled to receive each object file, for combining the object files to generate an executable file containing, for each reconfiguration directive, a reference to a bitstream describing the hardware organization of the selectively reconfigurable portion of the processing unit and a sequence of program instructions to be executed using the described hardware organization.

23. The compiling system of claim 21, further comprising:

a linker, coupled to receive each object file, for combining the object files to generate an executable file containing, for each reconfiguration directive, a bitstream describing the hardware organization of the selectively reconfigurable portion of the processing unit and a sequence of program instructions to be executed using the described hardware organization.

24. A computer program product comprising a computer-usable medium having computer-readable code embodied therein for generating a sequence of program instructions for use in a partially reconfigurable processing unit, comprising:

computer-readable program code devices configured to accept as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements;

computer-readable program code devices configured to identify a first configuration of the selectively reconfigurable portion of the processing unit to be used in executing the first subset of instruction statements;

computer-readable program code devices configured to identify a second configuration of the selectively reconfigurable portion of the processing unit to be used in executing the second subset of instruction statements; and

computer-readable program code devices configured to compile the first subset of instruction statements for execution using the first configuration and compiling the second subset of instruction statements for execution using the second configuration.

25. The computer program product of claim 24, further comprising:

computer-readable program code devices configured generate an executable file containing, for each reconfiguration directive, a reference to a bitstream describing the hardware organization of the selectively reconfigurable portion of the processing unit and a sequence of program instructions to be executed by the described hardware organization.

26. The computer program product of claim 24, further comprising:

computer-readable program code devices configured to generate an executable file including the compiled statements and further including, for each subset of instruction statements, a reference designating a bitstream representing a configuration of the selectively reconfigurable portion of the processing unit.

27. The computer program product of claim 24, further comprising:

computer-readable program code devices configured to generate an executable file including the compiled statements and further including, for each subset of instruction statements, a reference encoded according to an extended executable and linking format, the reference designating a bitstream representing a configuration of the selectively reconfigurable portion of the processing unit to be used in executing the subset of instruction statements.

28. The computer program product of claim 24, further comprising:

computer-readable program code devices configured to generate an executable file including the compiled statements and further including, for each subset of instruction statements, a bitstream representing a configuration of the selectively reconfigurable portion of the processing unit to be used in executing the subset of instruction statements.

29. The computer program product of claim 24, further comprising:

computer-readable program code devices configured to generate a first object file including the compiled statements and further including, for each subset of instruction statements, a reconfiguration code identifying the configuration to be used in executing the subset of instruction statements;

computer-readable program code devices configured to generate at least a second object file; and

computer-readable program code devices configured to link the generated object files to generate an executable file.

30. The computer program product of claim 29, further comprising:

computer-readable program code devices configured to perform memory alignment on the generated executable file according to alignment requirements.