Method of manufacturing self-aligned T-shaped gate through dual damascene

• US 6,077,733 A
• Filed: 09/03/1999
• Issued: 06/20/2000
• Est. Priority Date: 09/03/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Wei-Jen, Liu, Kuo-Chou, Chen, Yen-Ming, Lin, Shih-Chi
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): WHIPPLE, MATTHEW LAVERNE
• Application Number:
  US09/389,885
• Time in Patent Office: 291 Days
• Field of Search: 438/182, 438/197, 438/303, 438/585, 438/595
• US Class Current: 438/182
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A new method is provided to manufacture a T-shaped gate. A layer of insulation is deposited over a semiconductor surface (typically the surface of a substrate), a dual damascene structure containing a via opening and a conducting line trench is created in the layer of insulation. A layer of sacrificial oxide is grown and subsequently removed (preventing initial surface defects and providing protection during subsequent steps of etching). A layer of gate oxide is selectively grown on the bottom of the dual damascene opening. A layer of poly is deposited over the layer of insulation thereby including the dual damascene opening, the poly is planarized down to essentially the top of the dual damascene structure and the insulation is removed from above the surface of the substrate in the regions surrounding the dual damascene structure leaving the dual damascene structure in place.

Claims

1. A method of forming a T-shaped gate structure on the surface of a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate;

depositing a layer of insulating material over the surface of said substrate;

creating a trench in said insulating layer whereby said trench has the profile of a dual damascene structure;

temporarily applying a layer of sacrificial oxide over the surface of said dual damascene trench thereby including the surface of the surrounding substrate;

growing a layer of gate oxide at the bottom of said dual damascene trench;

depositing a layer of in-situ doped polysilicon inside said dual damascene trench thereby including the surface of the surrounding layer of insulation;

planarizing the surface of said layer of doped polysilicon essentially down to the top surface of said insulating layer; and

removing said insulating layer from above the surface of said substrate and adjacent to said dual damascene structure thereby leaving said dual damascene structure in place, whereby a portion of the insulating layer remains along the entire vertical sidewalls of said dual damascene structure.

2. The method of claim 1 wherein said depositing a layer of insulating material over the surface of said substrate is depositing a layer of a material that is selected from the group containing nitride or oxide, silicon dioxide (SiO₂), silicon nitride (Si₃ N₄), (SiN), siliconoxynitride (SiO_x N_y), or fluorinated silicon oxide (SiO_x F_y) said deposition using LPCVD, PECVD, or APCVD processing, at a temperature between about 400 to 800 degrees C. to a thickness between about 5000 to 10000 Angstrom.

3. The method of claim 1 wherein said creating a trench in said insulating layer is a process of photolithographic exposure of the surface of said layer of insulating material followed by an anisotrophcally etch of said layer of insulating material with a plasma gas containing carbon tetrofluoride (CF₄) as an etchant using a commercially available parallel plate RIE etcher or an Electron Cyclotron Resonance (ECR) plasma reactor.

4. The method of claim 1 wherein said temporarily applying a layer of sacrificial oxide is:

a thermal oxidation of the underlying silicon in a low power furnace using LPCVD or PECVD or APCVD procedures at a temperature within the range between 300 and 900 degrees C. for a time period within the range between 30 and 60 minutes to a thickness of between 50 and 200 Angstrom; and

removing said layer of sacrificial oxide by etching at a temperature of between about 120 and 160 degrees C. and a pressure of between about 0.30 and 0.40 Torr for a time of between about 33 and 39 seconds using a dry etch process.

5. The method of claim 1 wherein said temporarily applying a layer of sacrificial oxide is:

depositing a layer of material selected from the group containing an oxide or a nitride or TEOS (tetraethosiloxane), Plasma Enhanced TEOS (PETEOS), boron phosphate silicate glass (BPSG) or a preferred method using thermal oxide applied in a steam ambient; and

removing said layer of sacrificial oxide by etching at a temperature of between about 120 and 160 degrees C. and a pressure of between about 0.30 and 0.40 Torr for a time of between about 33 and 39 seconds using a dry etch process.

6. The method of claim 1 wherein said growing a layer of gate oxide at the bottom of said dual damascene trench is using a silicon dioxide or a composite oxide or a nitride oxide or a like gate dielectric grown in an oxidation steam ambient at a temperature between about 850 and 1000 degrees C. to a thickness between about 50 and 250 Angstrom.

7. The method of claim 1 wherein said depositing a layer of in situ doped polysilicon inside said dual damascene trench is depositing an in situ doped poly using LPCVD at a temperature between about 500 and 700 degrees C. to a thickness between about 4000 and 10000 angstrom, using silane as a source and with the addition of phosphine to provide the needed dopant.

8. The method of claim 1 wherein said planarizing the surface of said layer of doped polysilicon is a CMP process whereby said planarization is to proceed to essentially at or slightly below the surface of said layer of insulating material.

9. The method of claim 1 wherein said removing said insulating layer from above the surface of said substrate and adjacent to said dual damascene structure is an anisotropically etch using carbon tetrofluoride (CF₄) is an etchant gas using a commercially available parallel plate RIE etcher or an Electron Cyclotron Resonance (ECR) plasma reactor.

10. A method of forming a T-shaped gate structure on the surface of a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate;

depositing a layer of insulating material over the surface of said substrate using LPCVD, PECVD, or APCVD processing, at a temperature between about 400 to 800 degrees C. to a thickness between about 5000 to 10000 Angstrom;

creating a trench in said insulating layer whereby said trench has the profile of a dual damascene structure by photolithographic exposure of said insulating layer followed by applying an anisotropically etch with a plasma gas to the surface of said layer of insulating material;

temporarily applying a layer of sacrificial oxide by using a thermal oxidation of the underlying silicon or by a deposition of a suitable layer of material thereafter removing said layer of sacrificial oxide by etching;

selectively growing a layer of gate oxide at the bottom of said dual damascene trench;

depositing a layer of in-situ doped polysilicon inside said dual damascene trench thereby including the surface of the surrounding layer of insulating material using LPCVD at a temperature between about 500 and 700 degrees C. to a thickness between about 4000 and 10000 angstrom, using silane as a source and with the addition of phosphine to provide the needed dopant;

planarizing the surface of said layer of doped polysilicon using a CMP process whereby said planarization is to proceed to essentially at or slightly below the surface of said layer of insulating material; and

removing said insulating layer from above the surface of said substrate and adjacent to said dual damascene structure by performing an anisotropically etch of said insulating layer thereby leaving said dual damascene structure in place, whereby a portion of the insulating layer remains along the entire vertical sidewalls of said dual damascene structure.