Overlay target pattern and algorithm for layer-to-layer overlay metrology for semiconductor processing

• US 6,077,756 A
• Filed: 04/24/1998
• Issued: 06/20/2000
• Est. Priority Date: 04/24/1998
• Status: Expired due to Term

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Shiau, Gwo-Yuh, Lin, Hua-Tai, Wang, Pin-Ting
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/066,015
• Time in Patent Office: 788 Days
• Field of Search: 438/14, 438/401, 438/975, 438/FOR 435, 316/401, 257/797
• US Class Current: 438/401
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

Novel overlay targets and an algorithm metrology are provided that minimize the overlay measurement error for fabricating integrated circuits. The method is particularly useful for accurately measuring layer-to-layer overlay on a substrate having material layers, such insulating, polysilicon, and metal layers that have asymmetric profiles over the overlay targets resulting from asymmetric deposition or chemical/mechanically polishing. The novel method involves forming a triangular-shaped first overlay target in a first material layer on a substrate. A second material layer, having the asymmetric profile is formed over the first material layer. During patterning of the second material layer, smaller triangular-shaped second overlay target are etched. The vertices of the smaller second overlay targets are aligned to the midpoints of the sides of the first overlay target, which are less sensitive to the asymmetries in the second material layer. An algorithm is then used to determine the positions of the centroids of the first and second overlay targets, which coincide with perfect alignment. The distance between the two centroids is the degree of layer-to-layer misalignment of the two material layers.

Claims

1. A method for making novel overlay targets on a substrate and a means for measuring patterned layer-to-layer overlay alignment accuracy comprising the steps of:

providing a semiconductor substrate having a patterned first material layer with triangular-shaped first overlay targets recessed in said first material layer;

forming a patterned second material layer on said substrate having etched smaller triangular-shaped second overlay targets aligned over said first overlay targets, the vertices of said smaller triangular-shaped second overlay target aligned to the midpoints of sides of said triangular-shaped first overlay target, whereby the centroids of said first and second triangular overlay targets coincide when perfectly aligned;

providing said means consisting of an algorithm stored in permanent memory for measuring the distance between the centroids of said first and second triangular-shaped overlay targets and where said distance is a measure of misalignment of said patterned second material layer to said patterned first material layer.

2. The method of claim 1, wherein said triangular-shaped first and second overlay targets are equilateral triangular-shaped alignment targets.

3. The method of claim 1, wherein said triangular-shaped first and second alignment targets are isosceles triangular-shaped alignment targets.

4. The method of claim 1, wherein said material layers are polysilicon layers.

5. The method of claim 1, wherein said material layers are conducting layers.

6. The method of claim 1, wherein said material layers are insulating layers.

7. The method of claim 1, wherein said second material layer is a chemically/mechanically polished layer.

8. The method of claim 1, wherein said material layers are composed of any materials used in the fabrication of semiconductor devices.

9. The method of claim 1, wherein said permanent memory is a magnetic storage device and said algorithm is in computer program code.

10. A method for making novel overlay targets on a substrate and a means for measuring patterned layer-to-layer overlay alignment accuracy comprising the steps of:

providing a semiconductor substrate having a patterned first material layer with equilateral triangular-shaped first overlay targets recessed in said first material layer;

forming a patterned second material layer on said substrate having etched smaller equilateral triangular-shaped second overlay targets aligned over said first overlay targets, the vertices of said smaller triangular-shaped second alignment target aligned to the midpoints of sides of said triangular-shaped first alignment target, whereby the centroids of said first and second triangular overlay targets coincide when perfectly aligned;

providing said means consisting of an algorithm stored in permanent memory for measuring the distance between the centroids of said first and second triangular-shaped overlay targets and where said distance is a measure of misalignment of said patterned second material layer to said patterned first material layer.

11. The method of claim 10, wherein said patterned first and second material layers are any two consecutive material layers on a semiconductor integrated circuit on said substrate.

12. The method of claim 10, wherein said material layers are polysilicon layers.

13. The method of claim 10, wherein said material layers are conducting layers.

14. The method of claim 10, wherein said material layers are insulating layers.

15. The method of claim 10, wherein said second material layer is a chemically/mechanically polished layer.

16. The method of claim 10, wherein said material layers are composed of any materials used in the fabrication of semiconductor devices.

17. The method of claim 10 wherein said permanent memory is a magnetic storage device and said algorithm is computer program code.

18. Novel overlay targets on a substrate and a means for measuring patterned layer-to-layer overlay alignment accuracy comprised of:

a semiconductor substrate having a patterned first material layer with triangular-shaped first overlay targets recessed in said first material layer;

a patterned second material layer on said substrate having etched smaller triangular-shaped second overlay targets aligned over said first overlay targets, the vertices of said smaller triangular-shaped second alignment target aligned to the midpoints of sides of said triangular-shaped first alignment target, whereby the centroids of said first and second triangular overlay targets coincide when perfectly aligned;

said means consisting of an algorithm stored in permanent memory for measuring the distance between the centroids of said first and second triangular-shaped overlay targets and where said distance is a measure of misalignment of said patterned second material layer to said patterned first material layer.

19. The structure of claim 18, wherein said first and second triangular-shaped alignment targets are equilateral triangles in shape.

20. The structure of claim 18, wherein said first and second triangular-shaped alignment targets are isosceles triangles in shape.

21. The structure of claim 18, wherein said means is an algorithm encoded in permanent memory that measures the distance between the centroids of said first and second triangular targets and where said distance is a measure of the misalignment of said patterned second material layer to said patterned first material layer.