Dynamic test reordering

• US 6,078,189 A
• Filed: 09/28/1998
• Issued: 06/20/2000
• Est. Priority Date: 12/13/1996
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Noel, Leo A.
• Primary Examiner(s): Williams, Hezron
• Assistant Examiner(s): WIGGINS, JOHN DAVID
• Application Number:
  US09/162,006
• Time in Patent Office: 631 Days
• Field of Search: 324/765, 324/500, 324/537, 324/73.1, 364/468.17, 364/481, 364/580, 364/579, 73/865.8, 73/865.9, 73/865.5
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736

Abstract

A method of dynamically modifying a test program makes testing more efficient and less costly while avoiding errors from manual operations. In one embodiment the order of functional tests in the test program is dynamically changed based on the results of testing. Tests that have caused fails are moved earlier in the testing program without having to recompile the test program. Each functional test has an initialization step to set the chip in a state from which subsequent test vectors are run.

Claims

1. A method of testing a plurality of electronic devices for defect assessment, failure analysis, quality inspection and/or error observation comprising the steps of:

(a) providing a plurality of electronic devices to a tester for electrical testing;

(b) providing a plurality of individual tests that define a functional test block having a large number of test patterns used in a sequence during testing said plurality of electronic devices;

(c) testing a first electronic device of said plurality of devices with said plurality of functional tests, wherein an initializing step is done a plurality of times during said testing with said plurality of functional tests;

(d) obtaining a result of said testing step (c) in regards to passing or failing the individual functional tests and in case of any noted failure identifying the individual functional tests that failed;

(e) dynamically reordering the sequence for said plurality of functional tests within said functional test block based on said result in said step (d); and

(f) testing a second electronic device of said plurality of devices with said reordered functional tests, wherein an initializing step is done a plurality of times during said testing with said reordered functional tests.

2. A method as recited in claim 1, wherein said plurality of electronic devices of said step (a) comprise a plurality of semiconductor chips.

3. A method as recited in claim 2, wherein said plurality of semiconductor chips are part of a semiconductor wafer, said testing steps (a) to (f) being conducted before dicing said wafer.

4. A method as recited in claim 1, wherein said initializing step is done as a first step for each functional test.

5. A method as recited in claim 1, wherein in said testing step (b) said first electronic device passes a first test and then fails a second test and wherein said modifying step (d) comprises placing said second test before said first test.

6. A method as recited in claim 5, wherein each of said plurality of tests has a label, said testing step (c) further comprises storing said labels in sequential storage locations, said result obtaining step (d) comprising storing said label of said second test in a storage register, said reordering step (e) comprising the step of moving a label of said first test from a first storage location to a second storage location and moving said label of said second test from said storage register to said first position.

7. A method as recited in claim 6, wherein said label storing step comprises storing said labels in sequential storage locations before a test is performed on said first electronic device.

8. A method as recited in claim 6, wherein said label storing step comprises storing said labels in sequential storage locations as each test is performed on said first electronic device.

9. A method as recited in claim 5, wherein said second test is placed first.

10. A method as recited in claim 5, wherein said plurality of electronic devices comprise a built in self-test circuit, wherein said first test is accomplished by providing a first seed to the built in self-test circuit and said second test is accomplished by providing a second seed to the built in self-test circuit.

11. A method as recited in claim 1, wherein said electronic devices comprise a built in self-test circuit, wherein in said testing step (c) a first seed is provided to the built in self-test circuit before a second seed is provided and wherein in said testing step (f) said second seed is provided before said first seed.

12. A method as recited in claim 1, wherein, in said reordering step, said tests are reordered depending on their probability of causing a fail.

13. A method as recited in claim 1, wherein, in said reordering step, said tests are reordered depending on time for each of said tests to cause a fail.

14. A method as recited in claim 1, wherein said plurality of tests are included in a test program, said reordering step (e) being performed without recompiling said test program.

15. A method as recited in claim 1, further comprising probing said first electronic device and then probing said second electronic device, there being an index time there between, wherein said reordering step (e) is performed during said index time.

16. A method as recited in claim 1, further comprising the step of adding or deleting tests.

17. A method as recited in claim 1, wherein said plurality of tests are run at a first test condition and wherein said plurality of tests are repeated at a second test condition, wherein said reordering step (e) comprises the step of reordering said plurality of tests in said first test condition differently than in said second test condition.

18. A method as recited in claim 17, wherein each of said plurality of tests in said first test condition has a label, said testing step (c) further comprises storing said labels in first condition sequential storage locations, and wherein each of said plurality of tests in said second test condition has a label, said testing step (c) further comprises storing said labels in second condition sequential storage locations.

19. A method as recited in claim 1, wherein said plurality of semiconductor chips are scan design chips.