Substrate biasing circuit that utilizes a gated diode to set the bias on the substrate

• US 6,078,211 A
• Filed: 10/14/1998
• Issued: 06/20/2000
• Est. Priority Date: 10/14/1998
• Status: Expired due to Fees

• Current Assignee: Eastman Kodak Company
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kalnitsky, Alexander, Bergemont, Albert, Poplevine, Pavel
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/173,096
• Time in Patent Office: 615 Days
• Field of Search: 327/534, 327/535, 327/537, 327/564, 327/565, 327/566
• US Class Current: 327/534
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures

Abstract

A substrate biasing circuit utilizes a gated diode and a detection transistor to set the potential on a substrate to a desired substrate bias level. The potential on the substrate is set to the desired substrate bias level by applying a series of pulses to the gated diode. Each of the pulses applied to the gated diode causes a fixed amount of charge to be injected into the substrate. When the potential on the substrate has reached the desired substrate bias level, the pulses are insufficient to cause any further charge to be injected into the substrate. The detection transistor is used to determine when the potential is at the desired substrate bias level by biasing the transistor to output a current that corresponds to the potential on the substrate.

Claims

1. A substrate biasing circuit formed in a semiconductor material of a first conductivity type, the circuit comprising:

a first well of a second conductivity type formed in the semiconductor material;

a second well of the first conductivity type formed in the first well;

a gated diode formed in the second well;

a cell diode connected between the gated diode and ground; and

an oscillator connected to the gated diode.

2. The biasing circuit of claim 1 and further comprising:

a detection transistor formed in the second well, the detection transistor being spaced apart from the gated diode; and

a controller connected to the oscillator and the detection transistor.

3. The biasing circuit of claim 2 and further comprising a reset transistor connected to the second well and the controller.

4. The biasing circuit of claim 1 wherein the gated diode includes:

a diffusion region of the second conductivity type formed in the second well;

an inversion region defined in the second well, the inversion region adjoining the diffusion region;

a layer of oxide formed over the inversion region; and

a diode gate formed on the layer of oxide layer.

5. The biasing circuit of claim 2 wherein the detection transistor includes:

spaced-apart source and drain regions formed in the second well, the source and drain regions being spaced apart from the diffusion region and the inversion region;

a channel region defined in the second well between the source and drain regions;

a layer of gate oxide formed over the channel region; and

a detection gate formed on the layer of gate oxide over the channel region.

6. The biasing circuit of claim 4 wherein the oscillator is connected to the diode gate of the gated diode.

7. The biasing circuit of claim 4 wherein the cell diode is connected between the diffusion region and ground.

8. The biasing circuit of claim 2 wherein the oscillator outputs a series of pulses when commanded by the controller, and stops outputting the pulses when commanded by the controller.

9. A method for biasing a semiconductor material to a desired substrate bias level from an initial level with a substrate biasing circuit, the circuit comprising:

a first well of a second conductivity type which is formed in a semiconductor material of a first conductivity type;

a second well of the first conductivity type formed in the first well;

a gated diode formed in the second well;

a cell diode connected between the gated diode and ground; and

an oscillator connected to the gated diode;

the method comprising the step of applying pulses to the gated diode, the pulses being insufficient to cause charge to flow through the cell diode when the potential on the second well is equal to the desired substrate bias level.

10. The method of claim 9 wherein the biasing circuit further includes:

a detection transistor formed in the second well, the detection transistor being spaced apart from the gated diode; and

a controller connected to the oscillator and the detection transistor.

11. The method of claim 10 and further comprising the step of biasing the detection transistor to output a current when the potential on the second well is different from the desired substrate bias level, and prevent the current from being output from the detection transistor when the potential on the second well is equal to the desired substrate bias level.

12. The method of claim 11 and further comprising the step of stopping the oscillator from outputting pulses when no current is output from the detection transistor.

13. The method of claim 10 and further comprising the step of biasing the detection transistor to output a first current when the potential on the second well is equal to the desired substrate bias level, and a different current when the current from being output when the potential on the second well is different from the desired substrate bias level.

14. The method of claim 10 and further comprising a reset transistor connected to the second well and the controller.

15. The method of claim 14 and further comprising the steps of pulsing on reset transistor prior to the step of applying pulses to the gated diode.

16. The method of claim 10 wherein a current having a magnitude substantially equal to a first level flows from the detection transistor when the potential on the second well is at the desired substrate bias level.

17. The method of claim 16 and further comprising the step of commanding the oscillator to output pulses when the magnitude of the current changes from the first level, and commanding the oscillator to stop outputting pulses when the magnitude of the current is substantially equal to the first level.

18. The method of claim 17 wherein the first level is substantially zero.