Mutual exclusion of drawing engine execution on a graphics device

• US 6,078,339 A
• Filed: 02/10/1998
• Issued: 06/20/2000
• Est. Priority Date: 02/10/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sreenivas, Krishnan, Sreenivas, Aditya, Meinerth, Kim A.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/021,490
• Time in Patent Office: 861 Days
• Field of Search: 345/514, 345/501, 345/502, 345/506, 345/513, 345/522, 345/505
• US Class Current: 345/522
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A method for mutual exclusion of drawing engine execution on a graphics device is disclosed. The method checks a busy signal of an executing drawing engine. The executing drawing engine is one of a plurality of drawing engines of the graphics device and the only drawing engine executing out of the plurality of drawing engines. The method forwards a graphics instruction and associated data packet to a next drawing engine to execute after the executing drawing engine has completed execution. The next drawing engine to execute is one of the plurality of drawing engines.

Claims

1. A method for mutual exclusion of drawing engine execution on a graphics device having a plurality of drawing engines, comprising:

checking a plurality of busy signals from the corresponding plurality of drawing engines to determine whether all the plurality of drawing engines are idle or any one is busy;

forwarding a first graphics instruction and a first associated data packet to a first drawing engine only if all of the plurality of drawing engines are idle to ensure data coherency.

2. The method of claim 1 wherein prior to checking the plurality of busy signals from the corresponding plurality of drawing engines, receiving the first graphics instruction and the first associated data packet.

3. The method of claim 2 further comprising detecting assertion of a first busy signal from the first drawing engine executing the first graphics instruction.

4. The method of claim 3 further comprising receiving a second graphics instructions and a second associated data packet, and forwarding the second graphics instruction and the second associated data packet to a second drawing engine only if the first busy signal from the first drawing engine is deasserted and all other drawing engines are idle.

5. The method of claim 3 further comprising receiving a second graphics instruction and a second associated data packet, and forwarding the second graphics instruction and the second associated data packet to the first drawing engine only if the first busy signal from the first drawing engine is de-asserted and all other drawing engines are idle.

6. The method of claim 1 wherein prior to forwarding the first graphics instruction and the first associated data packet, decoding the graphics instruction to determine to which drawing engine the graphics instruction is to be forwarded.

7. The method of claim 6 wherein prior to forwarding the first graphics instruction and the first associated data packet, holding the first graphics instruction and the first associated data packet in a drawing engine queue.

8. The method of claim 1 for mutual exclusion of drawing engine execution on a graphics device having a plurality of drawing engines wherein the forwarding of the first graphics instruction and the first associated data packet to the first drawing engine only if all of the plurality of drawing engines are idle ensures data coherency into system memory over a data bus.

9. The method of claim 1 for mutual exclusion of drawing engine execution on a graphics device having a plurality of drawing engines wherein the forwarding of the first graphics instruction and the first associated data packet to the first drawing engine only if all of the plurality of drawing engines are idle ensures data coherency into local memory of the graphics device.

11. The apparatus of claim 8 wherein a graphics driver is coupled to the apparatus to generate and forward said graphics instruction and associated data packet to said command parser.

12. The apparatus of claim 11 wherein said command parser further comprises a drawing engine queue configured to holding said first graphics instruction and said first data packet received by said command parser from said graphics driver.

13. The apparatus of claim 12 wherein said one of the plurality of drawing engines asserts a busy signal to said command parser to indicate that said one of the plurality of drawing engines is executing and is not idle.

14. The apparatus of claim 13 wherein said one of the plurality of drawing engines de-asserts said busy signal to said command parser to indicate that it has completed execution and is idle.

15. The apparatus of claim 14 wherein said command parser further comprises a drawing engine execution logic coupled to said drawing engine queue and configured to fetch and forward a next graphics instruction and associated data packet to a next appropriate drawing engine to execute only when remaining said plurality of drawing engines are idle as indicated by their de-asserted busy signals.

10. An apparatus for mutual exclusion of drawing engine execution comprising:

a plurality of drawing engines to execute graphics instructions for a next frame for display, said plurality of drawing engines each to assert a busy signal on a corresponding busy signal line when executing a graphics instruction and de-assert the busy signal when the execution of the graphics instruction is completed; and

a command parser coupled to said plurality of drawing engines, said command parser to forward a first graphics instruction and a first data packet associated with the next frame to one of the plurality of drawing engines only when all the busy signals are de-asserted to ensure data coherency.

16. A computer system for mutual exclusion of drawing engine execution comprising:

a storage element configured to store a plurality of computer readable data, one of said plurality of computer readable data being a graphics driver configured to generate graphics instructions;

a plurality of drawing engines configured to execute said graphics instructions for a next frame for display, said plurality of drawing engines each to assert a busy signal on a corresponding busy signal line when executing a graphics instruction and de-assert the busy signal when the execution of the graphics instruction is completed; and

a command parser coupled to said plurality of drawing engines and said storage element, said command parser to forward a graphics instruction and a data packet associated with the next frame for display to one of the plurality of drawing engines only when all of the busy signals are de-asserted to ensure data coherency.

17. The system of claim 16 further comprising a graphics driver to generate and forward said graphics instruction and said data packet to said command parser.

18. The system of claim 17 wherein said command parser further comprises a drawing engine queue configured to holding said graphics instruction and said data packet received by said command parser from said graphics driver.

19. The system of claim 18 wherein said one of the plurality of drawing engines asserts a busy signal to said command parser to indicate that said one of the plurality of drawing engines is executing and is not idle.

20. The system of claim 19 wherein said one of the plurality of drawing engines de-asserts said busy signal to said command parser to indicate that it has completed execution and is idle.

21. The system of claim 20 wherein said command parser further comprises a drawing engine execution logic coupled to said drawing engine queue and configured to fetch and forward a next graphics instruction and associated data packet to a next appropriate drawing engine to execute while all remaining said plurality of drawing engines are idle as indicated by their de-asserted busy signals.

22. A method of providing data coherency to a frame of pixel data accessible by a plurality of drawing engines in a graphics processor, the method comprising:

controlling one of the plurality of drawing engines to operate on a frame of data in response to a first drawing engine instruction; and

controlling all other drawing engines of the plurality of drawing engines to not operate on the frame of data until the one of the plurality of drawing engines has completed operating on the frame of data in response to the first drawing engine instruction.

23. The method of claim 22 of providing data coherency to a frame of pixel data accessible by a plurality of drawing engines in a graphics processor, the method further comprising:

controlling another one of the plurality of drawing engines to operate on a frame of data in response to a second drawing engine instruction after the one of the plurality of drawing engines has completed operating on the frame of data in response to the first drawing engine instruction; and

controlling all other drawing engines of the plurality of drawing engines to not operate on the frame of data until the another of the plurality of drawing engines has completed operating on the frame of data in response to the second drawing engine instruction.

24. The method of claim 22 of providing data coherency to a frame of pixel data accessible by a plurality of drawing engines in a graphics processor, wherein, the controlling of the one and all other drawing engines of the plurality of drawing engines is responsive to the busy signal generated by each of the plurality of drawing engines.