Nonvolatile configuration cells and cell arrays

• US 6,078,521 A
• Filed: 08/30/1999
• Issued: 06/20/2000
• Est. Priority Date: 09/16/1996
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda U., Sansbury, James D.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/385,794
• Time in Patent Office: 295 Days
• Field of Search: 365/185.18, 365/185.19, 365/185.23, 365/185.24, 365/185.28
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Claims

1. A method of configuring a programmable memory element comprising:

grounding a tunnel diode, wherein the tunnel diode is coupled through a tunnel dielectric to a floating gate of the programmable memory element;

placing a VPP voltage on a control gate of the programmable memory element;

placing an assist voltage of about VDD or above on a drain of the programmable memory element;

passing the assist voltage through a pull-down device to a source of the programmable memory element; and

transferring electrons from the tunnel diode through the tunnel dielectric into the floating gate of the programmable memory element, thereby adjusting a threshold voltage of the programmable memory element so that a reasonable voltage on the control gate will not turn on the programmable memory element.

2. The method of claim 1 wherein the VPP voltage is a voltage in a range from about 11 volts to about 15 volts.

3. The method of claim 1 wherein the assist voltage is a voltage of about VDD.

4. The method of claim 1 wherein reasonable voltage is a voltage in a range from about VSS to about VDD.

5. The method of claim 1 wherein the reasonable voltage is generated by a charge pump or bias voltage generator.

6. The method of claim 1 wherein the pull-up resistor is formed using a thin film transistor.

7. The method of claim 1 wherein the pull-up resistor comprises a transistor.

8. The method of claim 1 wherein the programmable memory element is a Flash or EEPROM cell.

9. The method of claim 1 wherein the use of the assist voltage results in a higher threshold voltage than when the assist voltage is not used.