Timing synchronization and switchover in a network switch

• US 6,078,595 A
• Filed: 08/28/1997
• Issued: 06/20/2000
• Est. Priority Date: 08/28/1997
• Status: Expired due to Term

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Ascend Communications, Inc. (Nokia Corporation)
• Inventors: Branscomb, Brian, Hoch, Thomas A., Ganmukhi, Mahesh N., DeAngelis, Patrick L., Reed, Eric L., Schmidt, Raymond, Jones, John Patrick
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Nguyen, Kim T.
• Application Number:
  US08/920,250
• Time in Patent Office: 1,027 Days
• Field of Search: 370/219, 370/221, 370/225, 370/244, 370/522, 370/516, 370/503, 375/357, 375/371, 375/347, 375/226, 375/373, 375/376
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04Q 11/0421 Circuit arrangements therefor

Abstract

A data communications switch and method of operation are presently disclosed enabling flexible, selectable provision of a common timing signal for synchronized external communication through physical layer interfaces with other network devices, synchronized internal communications within the switch, and for uninterrupted synchronization of such communications. Synchronization of external communications is enabled by programmable selection from among plural potential timing references at redundant timing modules (TMs). An active TM provides a primary external synchronization clock; a standby TM provides a redundant timing function. Both TMs access the same references. A state signal indicates which synchronization clock is active. External interfaces derive timing from this distributed clock. Synchronized internal timing is provided by an internal clock and phase-locked loop (PLL) on each TM. The clock/PLL timing signal output is routed to other switch elements, enabling synchronized internal data transfer. Both interconnected TMs actively generate clock signals for external and internal use, enabling seamless timing switchover should conditions warrant a change in TMs.

Claims

1. A network switch for providing uninterrupted synchronous timing among each of plural modules within said network switch, comprising:

first and second timing modules, each having a local clock generator for generating an output clock signal and a phase locked loop for the generation of a respective timing signal based upon said output clock signal; and

a phase locked loop for each of said plural modules in said network switch, said plural modules enabling the switching of data through said network switch in synchronization with one of said timing signals,

said network switch having a first configuration wherein

said local clock generator of said first timing module is for providing said phase locked loop of said first timing module with said output clock signal for generation of said respective timing signal,

said phase locked loop of said first timing module for providing said respective timing signal to said phase locked loop of each of said plural modules, and to said phase locked loop of said second timing module for the generation of said respective timing signal,

said timing signal of said phase locked loop of said second timing module being unused by said phase locked loop of each of said plural modules when said first timing module-generated timing signal is used by said plural modules,

said network switch having a second configuration wherein

said local clock generator of said second timing module is for providing said phase locked loop of said second timing module with said output clock signal for generation of said respective timing signal,

said phase locked loop of said second timing module for providing said respective timing signal to said phase locked loop of each of said plural modules, and to said phase locked loop of said first timing module for the generation of said respective timing signal,

said timing signal of said phase locked loop of said first timing module being unused by said phase locked loops of each of said plural modules when said second timing module-generated timing signal is used by said plural modules.

2. A method of providing an internal timing signal to plural modules within a network switch for synchronizing data transfer within said switch, said switch comprising first and second timing modules, said method comprising the steps of:

generating a clock signal by a first local oscillator in said first timing module;

locking a phase locked loop of said first timing module to said clock signal of said local oscillator of said first timing module for providing a first timing module output;

locking a phase locked loop of said second timing module to said first timing module output for providing a second timing module output; and

using said first timing module output as said internal timing signal.

3. The method of claim 2, further comprising the steps of:

identifying a timing module switchover condition;

generating a clock signal by a second local oscillator in said second timing module;

locking said phase locked loop of said second timing module to said clock signal of said second timing module for providing said second timing module output;

locking said phase locked loop of said first timing module to said second timing module output; and

using said second timing module output as said internal timing signal.