Method of designing FPGAs for dynamically reconfigurable computing

• US 6,078,736 A
• Filed: 08/28/1997
• Issued: 06/20/2000
• Est. Priority Date: 08/28/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Guccione, Steven A.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): JONES, HUGH M
• Application Number:
  US08/919,531
• Time in Patent Office: 1,027 Days
• Field of Search: 395/500.17, 395/500.18
• US Class Current: 716/117
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

Claims

1. A method of configuring a field programmable gate array (FPGA), the FPGA being connected to a host processor for configuration thereby;

the method comprising the steps of;

a) programming the host processor with instructions in a high level programming language;

b) instantiating elements from a library of elements compatible with the high level programming language;

c) providing a compiler for the high level programming language to the host processor for generating executable code in response to the programmed instructions and the instantiated library elements, the executable code including compiled placement and routing information; and

d) configuring the FPGA from the host processor in response to the executable code.

2. The method recited in claim 1 wherein the FPGA is used for dynamically reconfigurable computing.

3. The method recited in claim 1 or claim 2 wherein the high level language is Java.

4. The method recited in claim 1 or claim 2 wherein the library comprises combinational logic elements.

5. The method recited in claim 1 or claim 2 wherein the library comprises flip-flop elements.

6. The method recited in claim 1 or claim 2 wherein the library comprises latch elements.

7. The method recited in claim 1 or claim 2 further comprising the step of:

e) using the library elements to generate a parameterized cell.

8. The method recited in claim 7 wherein the cell is a counter parameterized by the number of bits in the counter.

9. A method of configuring a field programmable gate array (FPGA) for dynamically reconfigurable computing;

the method comprising the steps of;

a) programming a host processor with instructions in a high level language;

b) providing a compiler for the high level programming language running on the host processor for generating executable code in response to the instructions, the executable code including compiled placement and routing information; and

c) connecting the host processor to the FPGA for dynamic reconfiguration programming of the FPGA by the host processor via the executable code.

10. The method recited in claim 9 wherein the high level language is Java.

11. The method recited in claim 9 further comprising the step of:

d) instantiating elements from a library of elements compatible with the compiler.

12. The method recited in claim 11 wherein the library comprises combinational logic elements.

13. The method recited in claim 11 wherein the library comprises flip-flop elements.

14. The method recited in claim 11 wherein the library comprises latch elements.