Method for accessing memory using overlapping accesses and early synchronous data transfer control
First Claim
1. A method for synchronously accessing memory, comprising the steps of:
- providing a first address for a first memory access during a first clock period;
activating a first control signal indicating an address phase of said first memory access during said first clock period;
activating a second control signal indicating a data phase of said first memory access during a second clock period subsequent to said first clock period;
receiving a first data element accessed by said first address during a third clock period immediately subsequent to said second clock period;
providing a second address for a second memory access during said third clock period; and
activating said first control signal indicating an address phase of said second memory access during said third clock period.
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Abstract
Accordingly, the present invention provides a method for synchronously accessing memory in order to improve the performance in systems which use memories with slower cores. A first address for a first memory access is provided during a first clock period. A first control signal to indicate an address phase of the first memory access is activated during the first clock period. A second control signal to indicate a data phase of the first memory access is activated during a second clock period subsequent to the first clock period. A first data element accessed by the first address is received during a third clock period immediately subsequent to the second clock period. A second address for a second memory access is provided during the third clock period. The first control signal indicating an address phase of the second memory access is activated during the third clock period.
18 Citations
17 Claims
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1. A method for synchronously accessing memory, comprising the steps of:
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providing a first address for a first memory access during a first clock period; activating a first control signal indicating an address phase of said first memory access during said first clock period; activating a second control signal indicating a data phase of said first memory access during a second clock period subsequent to said first clock period; receiving a first data element accessed by said first address during a third clock period immediately subsequent to said second clock period; providing a second address for a second memory access during said third clock period; and activating said first control signal indicating an address phase of said second memory access during said third clock period. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for synchronously accessing memory, comprising the steps of:
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providing a first address for a first memory access at least a first predetermined setup time before a first transition of a clock signal; activating a chip enable signal for said first memory access at least a second predetermined setup time before said first transition of said clock signal; activating an output enable signal indicating a data phase of said first memory access a third predetermined setup time before a second transition of said clock signal subsequent to said first transition of said clock signal; receiving a first data element accessed by said first address at a third transition of said clock signal subsequent to said second transition of said clock signal; providing a second address for a second memory access at least said first predetermined setup time before said third transition of said clock signal; and activating said first control signal indicating an address phase of said second memory access at least said second predetermined setup time before said third transition of said clock signal. - View Dependent Claims (9, 10)
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11. A method for an integrated circuit microprocessor to synchronously access memory, comprising the steps of:
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driving a first address for a first memory access during a first clock period; activating a first control signal indicating a data phase of said first memory access during a second clock period subsequent to said first clock period by a predetermined number of wait states; and receiving and latching a first data element accessed by said first address during a third clock period immediately subsequent to said second clock period; driving a second address for a second memory access during said third clock period; and activating said first control signal indicating an address phase of said second memory access during said third clock period. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification