Parallel data skew detecting circuit

• US 6,079,035 A
• Filed: 03/06/1998
• Issued: 06/20/2000
• Est. Priority Date: 09/01/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Osamu, Watanabe, Takayuki
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/035,924
• Time in Patent Office: 837 Days
• Field of Search: 714/700, 327/73, 327/514, 327/141, 327/261, 327/269, 327/393
• US Class Current: 714/700
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A sample signal is sequentially transported through a plurality of serial shift registers in respective data channels. The sample signal varies between a pair of levels, namely a first level and a second level, to resemble a step with respect to time. The shift registers are monitored by a skew detection circuit to identify the shift register that receives the sample signal at the time of a generated timing signal. Data signals are then passed through the recorded shift register while compensating for detected skew in parallel transmission data.

Claims

1. A parallel data skew detecting circuit, comprising:

a plurality of parallel data channels including a plurality of serial shift registers to transmit a sample signal;

a timing signal generating circuit to generate a timing signal in a predetermined period;

a skew storage circuit to record the shift register which receives the sample signal for the respective data channels when the timing signal is generated; and

a processing completion detecting circuit to detect that all of the data channels have received the sample signal within a skew detecting period defined by the number of the shift registers, and to output a completion signal upon completion of the detection, to thereby confirm that skew is detected.

2. The parallel data skew detecting circuit according to claim 1, wherein said sample signal comprises at least an edge which rises up to a data value level, and a constant level portion which maintains the data value level continuous to the edge.

3. The parallel data skew detecting circuit according to claim 1, wherein said timing signal generating circuit generates the timing signal to allow the shift register which receives the sample signal to be identified when all of the data channels receive the sample signal.

4. The parallel data skew detecting circuit according to claim 3, wherein said timing signal generating circuit receives a reset signal to reset the skew storage circuit.

5. The parallel data skew detecting circuit according to claim 1, further comprising:

an incomplete channel detecting circuit to detect the data channel in which the sample signal has passed through all of the shift registers when said processing completion detecting circuit fails to output the completion signal.

6. The parallel data skew detecting circuit according to claim 1, further comprising:

gate circuit to selectively allow output of a data signal from the shift register recorded in the skew storage circuit in the data channel.

7. The parallel data skew detecting circuit according to claim 1, wherein the data channels are connected to an optical converter circuit which converts an optical signal into an electric signal.