Ion implantation into a gate electrode layer using an implant profile displacement layer

• US 6,080,629 A
• Filed: 04/21/1997
• Issued: 06/27/2000
• Est. Priority Date: 04/21/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Wristers, Derick J., Hause, Frederick N., Gardner, Mark I., Fulford, H. Jim Jr., Moore, Bradley T.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/837,579
• Time in Patent Office: 1,163 Days
• Field of Search: 438/301, 438/303, 438/305, 438/162
• US Class Current: 438/301
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.

Claims

1. In a semiconductor process, a method of forming a gate electrode for an insulated gate field effect transistor (IGFET), said method comprising the steps of:

providing a gate dielectric layer on an underlying semiconductor body;

forming a gate electrode layer on the gate dielectric layer;

forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer;

implanting a first material into the combined displacement/gate electrode layer to form an implant profile of the first material within at least the gate electrode layer; and

removing regions of the combined displacement/gate electrode layer to form a gate electrode in remaining regions.

2. A method as in claim 1 wherein:

the removing step is performed before the first material implanting step; and

the first material implanting step is performed into the remaining regions of the combined displacement/gate electrode layer which form the gate electrode.

3. A method as in claim 1 further comprising the step of:

removing the entire displacement layer after the first material implanting step.

4. A method as in claim 1 wherein:

the first material implant profile substantially resides entirely within the gate electrode layer.

5. A method as in claim 1 wherein:

the first material implant profile substantially resides partially within the gate electrode layer and partially within the displacement layer.

6. A method as in claim 1 wherein:

the first material implant profile substantially resides partially within the gate electrode layer and partially within the displacement layer; and

the method further comprises the step of removing the displacement layer after the first material implanting step.

7. A method as in claim 1 wherein:

the first material implanting step is performed non-selectively into the combined displacement layer/gate electrode layer.

8. A method as in claim 1 wherein:

the implanting step is performed selectively into a first region of the combined displacement layer/gate electrode layer.

9. A method as in claim 8 further comprising the step of:

selectively implanting a second material into a second region of the combined displacement layer/gate electrode layer different from the first region, to form an implant profile of the second material within at least the gate electrode layer.

10. A method as in claim 1 wherein the displacement layer comprises:

a silicon-containing layer chosen from the group consisting of silicon nitride and polysilicon.

11. A method as in claim 1 wherein the displacement layer comprises:

an oxide-containing layer chosen from the group consisting of silicon oxide, silicon oxynitride, nitrogen-containing silicon oxide, nitrogen-containing silicon oxynitride, and tetraethylorthosilicate (TEOS).

12. A method as in claim 1 wherein the displacement layer comprises:

a polymer-based layer.

13. A method as in claim 1 wherein the displacement layer comprises:

a silicon-containing layer chosen from the group consisting of silicon nitride and polysilicon;

an etch-stop layer formed between the silicon-containing layer and the gate electrode layer.

14. A method as in claim 1 wherein:

the first material is chosen from the group consisting of an N-type dopant, a P-type dopant, and a nitrogen-containing material; and

the gate electrode layer comprises a polysilicon-based layer.

15. In a semiconductor process, a method of forming gate electrodes suitable for insulated gate field effect transistors (IGFET), said method comprising the steps of:

providing a gate dielectric layer on an underlying semiconductor body;

forming a polysilicon gate electrode layer having a thickness on the gate dielectric layer;

forming a displacement layer having a thickness on the gate electrode layer to form a combined displacement/gate electrode layer;

implanting a first material into a first region of the combined displacement/gate electrode layer to form therewithin an implant profile of the first material within at least the gate electrode layer;

implanting a second material into a second region of the combined displacement layer/gate electrode layer, to form therewithin an implant profile of the second material within at least the gate electrode layer;

removing regions of the combined displacement/gate electrode layer to form a first gate electrode within the first region and a second gate electrode within the second region.

16. A method as in claim 15 further comprising the step of:

masking, before the first material implanting step, the combined displacement layer/gate electrode layer to expose the first region thereof and to protect remaining regions thereof.

17. A method as in claim 16 further comprising the step of:

masking, before the second material implanting step, the combined displacement layer/gate electrode layer to expose the second region thereof and to protect remaining regions thereof.

18. A method as in claim 15 wherein:

the first material comprises arsenic; and

the second material comprises a boron-containing material.

19. A method as in claim 18 wherein:

the thickness of the gate electrode layer is between approximately 200 Å and

2500 Å

;

the first material implant profile substantially resides partially within the displacement layer and partially within the gate electrode layer; and

the second material implant profile substantially resides partially within the displacement layer and partially within the gate electrode layer.

20. A method as in claim 16 further comprising the step of:

etching, before the first material implanting step, the displacement layer within the exposed first region to reduce its thickness.

21. A method as in claim 15 further comprising the step of:

removing the displacement layer after the second material implanting step.

22. A method as in claim 20 wherein the displacement layer comprises:

an oxide-containing layer chosen from the group consisting of silicon oxide, silicon oxynitride, nitrogen-containing silicon oxide, nitrogen-containing silicon oxynitride, and tetraethylorthosilicate (TEOS).

23. A method as in claim 20 wherein the displacement layer comprises:

an etch-stop layer formed on the gate electrode layer; and

a silicon-containing layer formed on the etch-stop layer, said silicon-containing layer chosen from the group consisting of silicon nitride and polysilicon.

24. A method as in claim 23 wherein the etch-stop layer comprises:

a material chosen from the group consisting of silicon oxide and silicon oxynitride.

25. A method as in claim 23 wherein the etch-stop layer has a thickness in the approximate range from 30-200 Å

.

26. A method as in claim 19 wherein:

the combined displacement layer/gate electrode layer is formed to a thickness between approximately 2000 and 2500 Å

.

27. A method as in claim 19 wherein:

the first and second material implanting steps are performed using an acceleration energy within the approximate range of 5-25 KeV.

28. A method as in claim 15 further comprising the step of:

etching, after the gate electrode layer forming step, the gate electrode layer within the first region to reduce its thickness.

29. A method as in claim 15 further comprising the step of:

removing the displacement layer after the second material implanting step;

wherein the gate electrode layer comprises a lower portion of a particular polysilicon layer; and

wherein the displacement layer comprises an upper portion of the particular polysilicon layer.

30. In a semiconductor process, a method of forming gate electrodes suitable for insulated gate field effect transistors (IGFET), said method comprising the steps of:

providing a gate dielectric layer on an underlying semiconductor body;

forming a gate electrode layer on the gate dielectric layer, said gate electrode layer having a first thickness within a first region and having a second thickness within a second region;

implanting a first material into the first region of the gate electrode layer to form therewithin an implant profile of the first material within at least the gate electrode layer;

implanting a second material into the second region of the gate electrode layer, to form therewithin an implant profile of the second material within at least the gate electrode layer;

removing regions of the gate electrode layer to form a first gate electrode within the first region and a second gate electrode within the second region.

31. A method as in claim 30 further comprising the step of:

forming, before the first material implanting step, a displacement layer having thickness on the gate electrode layer, to form a combined displacement/gate electrode layer; and

wherein the first and second material implanting steps are performed through the displacement layer.

32. A method as in claim 31 further comprising the step of:

masking, before the first material implanting step, the combined displacement layer/gate electrode layer to expose the first region thereof and to protect remaining regions thereof.

33. A method as in claim 32 further comprising the step of:

masking, before the second material implanting step, the combined displacement layer/gate electrode layer to expose the second region thereof and to protect remaining regions thereof.

34. A method as in claim 33 further comprising the step of:

removing the displacement layer after the second material implanting step and before the gate electrode layer removing step.

35. A method as in claim 34 wherein:

the first material comprises arsenic; and

the second material comprises a boron-containing material.

36. A method as in claim 30 further comprising the step of:

removing upper portions of the gate electrode layer to form a thinner gate electrode layer.

37. A method as in claim 30 further comprising the step of:

etching, after the gate electrode layer forming step, the gate electrode layer within the first region to reduce its thickness.

38. A method as in claim 37 further comprising the step of:

removing the displacement layer after the second material implanting step.