Ion implantation into a gate electrode layer using an implant profile displacement layer
First Claim
1. In a semiconductor process, a method of forming a gate electrode for an insulated gate field effect transistor (IGFET), said method comprising the steps of:
- providing a gate dielectric layer on an underlying semiconductor body;
forming a gate electrode layer on the gate dielectric layer;
forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer;
implanting a first material into the combined displacement/gate electrode layer to form an implant profile of the first material within at least the gate electrode layer; and
removing regions of the combined displacement/gate electrode layer to form a gate electrode in remaining regions.
3 Assignments
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Accused Products
Abstract
A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
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Citations
38 Claims
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1. In a semiconductor process, a method of forming a gate electrode for an insulated gate field effect transistor (IGFET), said method comprising the steps of:
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providing a gate dielectric layer on an underlying semiconductor body; forming a gate electrode layer on the gate dielectric layer; forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer; implanting a first material into the combined displacement/gate electrode layer to form an implant profile of the first material within at least the gate electrode layer; and removing regions of the combined displacement/gate electrode layer to form a gate electrode in remaining regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. In a semiconductor process, a method of forming gate electrodes suitable for insulated gate field effect transistors (IGFET), said method comprising the steps of:
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providing a gate dielectric layer on an underlying semiconductor body; forming a polysilicon gate electrode layer having a thickness on the gate dielectric layer; forming a displacement layer having a thickness on the gate electrode layer to form a combined displacement/gate electrode layer; implanting a first material into a first region of the combined displacement/gate electrode layer to form therewithin an implant profile of the first material within at least the gate electrode layer; implanting a second material into a second region of the combined displacement layer/gate electrode layer, to form therewithin an implant profile of the second material within at least the gate electrode layer; removing regions of the combined displacement/gate electrode layer to form a first gate electrode within the first region and a second gate electrode within the second region. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. In a semiconductor process, a method of forming gate electrodes suitable for insulated gate field effect transistors (IGFET), said method comprising the steps of:
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providing a gate dielectric layer on an underlying semiconductor body; forming a gate electrode layer on the gate dielectric layer, said gate electrode layer having a first thickness within a first region and having a second thickness within a second region; implanting a first material into the first region of the gate electrode layer to form therewithin an implant profile of the first material within at least the gate electrode layer; implanting a second material into the second region of the gate electrode layer, to form therewithin an implant profile of the second material within at least the gate electrode layer; removing regions of the gate electrode layer to form a first gate electrode within the first region and a second gate electrode within the second region. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38)
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Specification