Composite trench-fin capacitors for DRAM

• US 6,081,008 A
• Filed: 06/20/1997
• Issued: 06/27/2000
• Est. Priority Date: 02/14/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Rostoker, Michael D.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US08/879,341
• Time in Patent Office: 1,103 Days
• Field of Search: 257/303, 257/301, 257/296
• US Class Current: 257/303
• CPC Class Codes: H10B 12/377 having a storage electrode extension located over the transistor

Abstract

A semiconductor memory device capacitor is disclosed which has a trench capacitor portion provided in a semiconductor substrate and a fin capacitor portion provided above the substrate. The trench capacitor portion includes (i) a trench extending from an upper surface of the semiconductor substrate downwardly into the substrate, and (ii) an electrically conductive trench electrode provided interior to the trench. And the fin capacitor portion includes (i) a fin electrode having a body portion and two or more electrically conductive fins extending outwardly from the body portion, (ii) a fin dielectric layer conformally coating the two or more electrically conductive fins, and (iii) a cell electrode surrounding and in intimate contact with the two or more electrically conductive fins.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate having an upper surface;

a trench capacitor portion provided in said substrate and including

a trench extending from said upper surface downwardly into said semiconductor substrate, and

an electrically conductive trench electrode provided interior to said trench; and

a fin capacitor portion provided on said substrate and including

a fin electrode having a body portion and two or more electrically conductive fins extending outwardly from said body portion,

a fin dielectric layer conformally coating said two or more electrically conductive fins, and

a cell electrode surrounding and in intimate capacitive contact with said two or more electrically conductive fins.

2. The semiconductor memory device of claim 1, wherein said trench electrode and said fin electrode are conductively coupled and together form one electrode of a cell capacitor of said semiconductor memory device.

3. The semiconductor memory device of claim 2, wherein said trench electrode includes a cavity extending from said fin electrode downwardly into said trench electrode, and wherein said fin dielectric layer conformally coats said cavity.

4. The semiconductor memory device of claim 3, wherein said cell electrode extends downwardly into said cavity, such that the cell electrode forms a second electrode of said cell capacitor of said semiconductor memory device.

5. The semiconductor memory device of claim 1, further comprising a trench dielectric layer conformally coating said trench and intimately contacting said electrically conductive trench electrode.

6. The semiconductor memory device of claim 5, wherein a portion of said semiconductor substrate adjacent to said trench forms one capacitor electrode of said trench capacitor portion, and wherein said trench electrode forms a counter electrode of said trench capacitor portion.

7. The semiconductor memory device of claim 1 wherein the fin capacitor portion includes three or more electrically conductive fins.

8. An integrated circuit incorporating active devices and capacitors in a semiconductor substrate having an upper surface, the integrated circuit comprising:

a plurality of cell capacitors, each including

(a) a trench capacitor portion provided in said substrate and having (i) a trench extending from said upper surface downwardly into said semiconductor substrate, and (ii) an electrically conductive trench electrode provided interior to said trench; and

(b) a fin capacitor portion provided on said substrate and having (i) a fin electrode having a body portion and two or more electrically conductive fins extending outwardly from said body portion, (ii) a fin dielectric layer conformally coating said two or more electrically conductive fins, and (iii) a cell electrode surrounding and in intimate capacitive contact with said two or more electrically conductive fins; and

a plurality of active devices arranged in a predefined circuit configuration with at least some of said plurality of cell capacitors.

9. The integrated circuit of claim 8 wherein the integrated circuit is a dynamic random access memory comprised of dynamic memory cells, each of which includes one of said cell capacitors and a pass transistor connected in series.

10. The integrated circuit of claim 9 wherein the integrated circuit includes at least about 1.5 billion dynamic memory cells on said semiconductor substrate which semiconductor substrate is monocrystalline silicon.

11. The integrated circuit of claim 10 wherein the integrated circuit includes at least about 2 billion dynamic memory cells on said semiconductor substrate which semiconductor substrate is monocrystalline silicon.

12. The integrated circuit of claim 8, wherein said trench electrode and said fin electrode are electrically coupled and together form one cell electrode of each cell capacitor.

13. The integrated circuit of claim 12, wherein said trench electrode includes a cavity extending from said fin electrode downwardly into said trench electrode, and wherein said fin dielectric layer conformally coats said cavity.

14. The integrated circuit of claim 13, wherein said cell electrode extends downwardly into said cavity, such that the cell electrode forms a second electrode of each cell capacitor.

15. The integrated circuit of claim 8, further comprising a trench dielectric layer conformally coating said trench and intimately contacting said electrically conductive trench electrode.

16. The integrated circuit of claim 15, wherein a portion of said semiconductor substrate adjacent to said trench forms one capacitor electrode of said trench capacitor portion, wherein said trench electrode forms a counter electrode of said trench capacitor portion.

17. A digital system having a plurality of semiconductor integrated circuits, each incorporating active devices and cell capacitors in a semiconductor substrate having an upper surface, the digital system integrated circuits each comprising:

a plurality of cell capacitors, each including

(a) a trench capacitor portion provided in said substrate and having (i) a trench extending from said upper surface downwardly into said semiconductor substrate, and (ii) an electrically conductive trench electrode provided interior to said trench; and

(b) a fin capacitor portion provided on said substrate and having (i) a fin electrode having a body portion and two or more electrically conductive fins extending outwardly from said body portion, (ii) a fin dielectric layer conformally coating said two or more electrically conductive fins, and (iii) a cell electrode surrounding and in intimate capacitive contact with said two or more electrically conductive fins; and

a plurality of active devices arranged in a predefined circuit configuration with at least some of said plurality of capacitors.

18. The digital system of claim 17 wherein the integrated circuits are DRAMs and the digital system is a multichip memory module.

19. The integrated circuit of claim 17, wherein said trench electrode and said fin electrode are electrically coupled and together form one cell electrode of each cell capacitor.

20. The integrated circuit of claim 19, wherein said trench electrode includes a cavity extending from said fin electrode downwardly into said trench electrode, and wherein said fin dielectric layer conformally coats said cavity.

21. The digital system of claim 17 wherein at least one of the integrated circuits includes at least about 1.5 billion dynamic memory cells on said semiconductor substrate which semiconductor substrate is monocrystalline silicon.