High voltage mosfet structure

• US 6,081,009 A
• Filed: 11/10/1997
• Issued: 06/27/2000
• Est. Priority Date: 11/10/1997
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Neilson, John M. S.
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/966,867
• Time in Patent Office: 960 Days
• Field of Search: 257/341, 257/495, 257/653
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 257/927 Different doping levels in different parts of PN junction to produce shaped depletion layer

Abstract

A high voltage MOSFET with low on-resistance and a method of lowering the on-resistance for a specific device breakdown voltage of a high voltage MOSFET. The MOSFET includes a blocking layer of a first conductivity type having vertical sections of a second conductivity type or the blocking layer may include alternating vertical sections of a first and second conductivity type.

Claims

1. A vertically conducting high voltage MOSFET having a voltage supporting region comprising a horizontal layer having an avalanche breakdown voltage, wherein if the electric field in said layer reaches said avalanche breakdown voltage, the electric field over substantially the entire vertical thickness of said layer reaches said avalanche breakdown voltage.