Semiconductor component having a semiconductor chip mounted to a chip mount

• US 6,081,037 A
• Filed: 06/22/1998
• Issued: 06/27/2000
• Est. Priority Date: 06/22/1998
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lee, Tien-Yu Tom, Hause, James Vernon
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/102,092
• Time in Patent Office: 736 Days
• Field of Search: 257/706, 257/707, 257/779, 257/787, 257/718, 257/719, 257/691, 257/778
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A semiconductor device (30) includes a semiconductor chip (11) flip chip mounted on a substrate (21) and a thermally conductive chip mount (31) mounded on the semiconductor chip (11). The thermally conductive chip mount (31) has a cavity (34) formed therein. The semiconductor chip (11) fits in the cavity (34) and is thermally coupled to the thermally conductive chip mount (31). The thermally conductive chip mount (31) provides a thermal conduction path to dissipate heat generated in the semiconductor chip (11) through its sidewalls (15, 16, 17, 18).

Claims

1. A semiconductor device, comprising:

a semiconductor chin having a first surface, a second surface, and a sidewall;

a chip mount having a first surface, a second surface, and a cavity therein, the cavity having an edge coupled to the sidewall of said semiconductor chip, and wherein the cavity in said chip mount extends from the first surface of said chip mount to the second surface of said chip mount;

wherein the second surface of said chip mount is substantially coplanar with the second surface of said semiconductor chip; and

a substrate having a major surface, wherein the first surface of said semiconductor chip is attached to a first portion of the major surface of said substrate via a solder bump.

2. The semiconductor device of claim 1, wherein the edge of the cavity in said chip mount compresses the sidewall of said semiconductor chip.

3. The semiconductor device of claim 1, wherein the edge of the cavity in said chip mount is coupled to the sidewall of said semiconductor chip via an epoxy.

4. The semiconductor device of claim 1, wherein the first surface of said chip mount is coupled to a second portion of the major surface of said substrate.

5. The semiconductor device of claim 1, further comprising a heat spreader overlying the second surface of said semiconductor chip and the second surface of said flag.