Field programmable gate array having testable antifuse programming architecture and method therefore

• US 6,081,129 A
• Filed: 09/17/1997
• Issued: 06/27/2000
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Kolze, Paige A., Apland, James M.
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/931,893
• Time in Patent Office: 1,014 Days
• Field of Search: 326/37-41
• US Class Current: 326/41
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. To test the integrity of programming conductors, programming transistors, routing wire segments and a combinatorial portion of a logic module of the unprogrammed FPGA (see FIG. 16), a combination of digital logic values is supplied onto the inputs of the combinatorial portion in a test mode. A defect is determined to exist if the correct digital value is not then output by the combinatorial portion. The digital value output by the combinatorial portion is captured in the flip-flop of the logic module and is shifted out of the FPGA in a scan out test mode. A programming transistor, programming conductor and routing wire segment structure is also disclosed which facilitates such testing. In one embodiment (see FIG. 15), the gate of no programming transistor coupled to an output routing wire segment of the logic module (such as transistor 216) is permanently connected to the gate of any programming transistor coupled to an input routing wire segment of the logic module (such as transistors 200, 201 and 202).

Claims

1. A field programmable gate array, comprising:

a plurality of programming conductors extending parallel to one another in a first dimension;

a plurality of logic modules disposed in a row extending in said first dimension parallel to said plurality of programming conductors;

a plurality of first routing wire segments extending parallel to one another in a second dimension perpendicular to said first dimension, some of said first routing wire segments I being coupled to inputs of one of said logic modules, the others of said first routing wire segments O being coupled to outputs of said one of said logic modules;

a plurality of second routing wire segments extending parallel to one another in said first dimension and crossing said plurality of first routing wire segments;

a plurality of antifuses disposed to programmably couple selected ones of said first and second routing wires segments together; and

a plurality of programming transistors, each of said programming transistors having a first electrode coupled to a respective one of said first routing wire segments, each of said programming transistors having a second electrode coupled to one of said plurality of programming conductors, each of said programming transistors having a control electrode, wherein none of the control electrodes of the programming transistors coupled to the routing wire segments O is permanently connected to the control electrode of any programming transistor coupled to a routing wire segment I.

2. The field programmable gate array of claim 1, wherein the second electrode of the programming transistor coupled to one of said first routing wire segments O is coupled to the same programming conductor that the second electrode of the programming transistor coupled to one of said first routing wire segments I is coupled.

3. The field programmable gate array of claim 2, wherein said one of said logic modules comprises a sequential logic element, said one of said first routing wire segments O being coupled to an output of said sequential logic element.

4. The field programmable gate array of claim 2, wherein said sequential logic element has a scan input lead which is coupled to an output of a sequential logic element of another logic module of said field programmable gate array.

5. A method of testing an unprogrammed field programmable gate array employing antifuses, comprising:

supplying digital values onto inputs V of a combinatorial portion of a logic module so that an output of the combinatorial portion carries a digital value W, the output of the combinatorial portion being coupled to an output of the logic module;

conducting the digital value W from the output of the logic module via a first routing wire segment and through a first programming transistor to a programming conductor, the first routing wire segment extending in a first dimension and the programming conductor extending in a second dimension perpendicular to said first dimension; and

conducting the digital value W from the programming conductor through a second programming transistor and through a second routing wire segment to an input X of the logic module, the second routing wire segment extending parallel to said first routing wire segment, said digital value W determining a digital value Y present on an input lead of a sequential logic element of said logic cell.

6. The method of testing an unprogrammed field programmable gate array of claim 5, further comprising:

clocking said digital value Y into said sequential logic element and using a digital value Z output from said sequential logic element to test said first programming transistor.

7. The method of testing an unprogrammed field programmable gate array of claim 6, further comprising:

using a scan chain of flip-flops to clock said digital value Z out of said field programmable gate array.

8. The method of testing an unprogrammed field programmable gate array of claim 5, wherein said logic module also comprises a multiplexer, an output lead of said multiplexer being coupled to said input lead of said sequential logic element, said multiplexer not being a part of said combinatorial portion of said logic module.

9. The method of testing an unprogrammed field programmable gate array of claim 8, wherein said multiplexer has a first data input lead, a second data input lead, a select input lead and an output lead, the first data input lead of the multiplexer being directly connected to the output of the logic module.

10. A method of testing a programmable device, the programmable device comprising a plurality of logic modules and a programmable interconnect structure employing antifuses, each of the logic modules having a sequential logic element with a scan input lead and a scan output lead, the method comprising:

(a) outputting a digital signal from a first logic module of the programmable device;

(b) conducting the digital signal through a programming conductor of the programmable device and back into the first logic module via a routing wire segment;

(c) capturing the digital signal in a sequential logic element of the first logic module; and

(d) conducting the digital signal from the first logic module via a scan output lead of the sequential logic element of the first logic module and into a second logic module via a scan input lead of a sequential logic element of the second logic module.

11. The method of claim 10, wherein the digital signal passes through combinatorial logic in the first logic module after step (b) and prior to being captured in step (c).

12. The method of claim 11, wherein the combinatorial logic inverts the digital signal.

13. The method of claim 12, wherein the combinatorial logic comprises an AND gate having an inverting input.

14. The method of claim 10, wherein the programmable device comprises a programming driver, the programming driver being coupled to the programming conductor.

15. The method of claim 10, wherein the antifuses of the programmable interconnect structure are unprogrammed during steps (a), (b), (c) and (d).