Logical amplitude level conversion circuit, liquid crystal device and electronic apparatus

• US 6,081,131 A
• Filed: 02/09/1998
• Issued: 06/27/2000
• Est. Priority Date: 11/12/1997
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Ishii, Kenya
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/020,912
• Time in Patent Office: 869 Days
• Field of Search: 326/80, 326/68, 326/81, 326/83, 327/333, 345/87, 345/92, 345/204
• US Class Current: 326/68
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS

Abstract

A logic amplitude level converter circuit of the present invention includes voltage biasing means for obtaining a signal being amplified swinging relative to the logic threshold voltage of an output-stage buffer circuit in response to the high-low level change of an input signal having a low logic amplitude, a pulse amplifier circuit for obtaining a high logic amplitude signal by pulse-amplifying the signal being amplified, and the output-stage buffer circuit for obtaining an inverted signal of the high logic amplitude signal in response to the high logic amplitude signal as an input.

Claims

1. A logic amplitude level converter circuit comprising:

voltage biasing means obtaining a signal being amplified, the signal swinging relative to a logic threshold voltage of an output-stage buffer circuit as a reference, in response to a high-low level change of a low logic amplitude input signal; and

a pulse amplifier circuit obtaining a high logic amplitude signal by pulse-amplifying the signal being amplified;

the output-stage buffer circuit obtaining an inverted signal in response to the high logic amplitude signal as an input.

2. The logic amplitude level converter circuit according to claim 1, wherein the voltage biasing means comprises:

a logic threshold value generator circuit generating the logic threshold voltage of the output-stage buffer circuit; and

a logic threshold value shift circuit for obtaining the signal being amplified that, with the generated logic threshold voltage as a DC bias, adjusts an offset voltage to the DC bias in response to the high-low level change of the low logic amplitude input signal.

3. The logic amplitude level converter circuit according to claim 2, wherein the logic threshold value generator circuit is constructed by connecting in a diode configuration a dummy inverter of complementary transistors that are manufactured in a structure substantially identical to a structure of the output-stage buffer circuit.

4. The logic amplitude level converter circuit according to claim 2, wherein the logic threshold value shift circuit comprises:

a mirror current transistor that, along with the logic threshold value generator circuit, constitutes a current mirror circuit;

a diode-configured offset voltage generator transistor connected in series with the mirror current transistor, with a source of the offset voltage generator transistor as an input terminal for the low logic amplitude input signal and with a drain of the offset voltage generator transistor as an output terminal; and

DC bias setting means connected in parallel with the offset voltage generator transistor.

5. The logic amplitude level converter circuit according to claim 4, wherein the DC bias setting means is a resistance element.

6. The logic amplitude level converter circuit according to claim 4, wherein the DC bias setting means is a ON-resistance of a transistor.

7. The logic amplitude level converter circuit according to claim 2, further comprising voltage holding means for holding the logic threshold voltage.

8. The logic amplitude level converter circuit according to claim 7, wherein the voltage holding means is a capacitor formed between an output wiring layer of the logic threshold value generator circuit and a power supply wiring layer.

9. The logic amplitude level converter circuit according to claim 8, wherein the capacitor is an interlayer capacitor that includes an overlap region where a wide wiring line of the output wiring layer and the power supply wiring layer run in parallel with an interlayer insulating film interposed therebetween.

10. The logic amplitude level converter circuit according to claim 4, wherein the pulse amplifier circuit is a current-mirror type pulse amplifier circuit that comprises:

an input transistor for variably controlling current flowing through a current-source transistor; and

a load transistor for variably controlling mirror current flowing through a mirror current transistor;

the output terminal being connected to a gate of the input transistor while the input terminal is connected to a source of the load transistor; and

the pulse amplifier circuit comprising a load value variable control circuit that inverts the high-low level of the voltage at the output terminal and feeds the inverted signal to a gate of the load transistor as a control signal.

11. The logic amplitude level converter circuit according to claim 10, wherein the load value variable control circuit comprises:

a mirror current transistor that, along with the logic threshold value generator circuit, constitutes a current mirror circuit; and

a drive transistor connected in series with the mirror current transistor, with a voltage at the output terminal as a gate voltage and with a drain voltage as the control signal.

12. The logic amplitude level converter circuit according to claim 4, wherein the pulse amplifier circuit is a current-mirror type pulse amplifier circuit that comprises:

an input transistor for variably controlling current flowing through a current-source transistor; and

a load transistor for variably controlling mirror current flowing through a mirror current transistor;

the output terminal being connected to a gate of the input transistor while a low logic amplitude input signal of opposite phase to a first input signal is coupled to a source of the input transistor; and

the pulse amplifier circuit comprising a load value variable control circuit that offsets a voltage of the opposite phase input signal and applies the offset voltage to a gate of the load transistor as a control signal.

13. The logic amplitude level converter circuit according to claim 4, wherein the pulse amplifier circuit is a flip-flop type pulse amplifier circuit that comprises:

a first transistor for controlling a switch of one transistor of a flip-flop to turn and off the one transistor; and

a second transistor for controlling another transistor of the flip-flop to turn on and off the another transistor, with the output terminal connected to a gate of the first transistor; and

the pulse amplifier circuit comprising a load value variable control circuit that offsets a voltage of the opposite phase input signal and applies the offset voltage to a gate of the second transistor as a control signal.

14. The logic amplitude level converter circuit according to claim 12, wherein the load value variable control circuit comprises:

a mirror current transistor that, along with the logic threshold value generator circuit, constitutes a current mirror circuit;

a diode-configured offset voltage generator transistor connected in series with the mirror current transistor, with a source of the offset voltage generator transistor as an input terminal for the opposite phase input signal and with a drain of the offset voltage generator transistor as an output terminal for the control signal; and

a DC bias setting transistor connected in parallel with the offset voltage generator transistor.

15. A liquid-crystal device comprising:

a liquid crystal interposed between a pair of substrates;

a pixel assembly arranged in a matrix of transistors with pixel electrodes respectively connected to the transistors on one of the substrates;

a drive circuit arranged on one of the substrates for controlling the supply of a signal to the pixel assembly; and

a clock interface arranged on one of the substrates that supplies the drive circuit with a clock signal, the clock interface comprising the logic amplitude level converter circuit according to claim 1.

16. An electronic apparatus comprising the liquid-crystal device according to claim 15.

21. The logic amplitude level converter circuit according to claim 1, logic threshold voltages of CMOS circuits in the pulse amplifier circuit coinciding with the logic threshold voltage of the output-stage buffer circuit.

17. A logic amplitude level converter circuit including a voltage level converter circuit which converts an input signal of a relatively low logic amplitude into an output signal having a relatively high logic amplitude, and an output circuit for inverting the output signal from the voltage level converter circuit, the voltage level converter circuit comprising:

a logic threshold value shift circuit that receives the input signal and generates a signal being converted, for causing the input signal to swing respect to a logic threshold voltage of the output circuit as a reference; and

an amplifier circuit for amplifying the signal being converted.

18. The logic amplitude level converter circuit according to claim 17, further comprising a logic threshold value generator circuit for generating the logic threshold voltage of the inverter circuit, and a circuit current value being controlled according to the logic threshold voltage in the logic threshold value shift circuit.

22. The logic amplitude level converter circuit according to claim 17, logic threshold voltages of CMOS circuits in the amplifier circuit coinciding with the logic threshold voltage of the output circuit.

19. A logic amplitude level converter circuit including a voltage level converter converting an input signal having a relatively low logic amplitude into an output signal having a relatively high logic amplitude, and an output circuit for inverting the output signal from the voltage level converter, the voltage level converter comprising:

an input terminal for the input signal;

a first transistor which inputs a logic threshold voltage of the output circuit to its gate;

electrically parallel-connected second and third transistors that are electrically connected in series between the input terminal and the first transistor, a gate of the second transistor inputting the logic threshold voltage;

an electrical node of the first transistor and the second transistor, a gate of the third transistor being connected to the electrical node; and

an amplifier for converting an output from the electrical node into an output signal having the relatively high logic amplitude.

20. A logic amplitude level converter circuit according to claim 19, wherein a capacitor formed relative to a potential of a power supply is attached to the gates of the first and second transistors.

23. The logic amplitude level converter circuit according to claim 19, logic threshold voltages of CMOS circuits in the amplifier coinciding with the logic threshold voltage of the output circuit.