Wear leveling techniques for flash EEPROM systems

• US 6,081,447 A
• Filed: 03/05/1999
• Issued: 06/27/2000
• Est. Priority Date: 09/13/1991
• Status: Expired due to Fees

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation), Western Digital Corporation
• Inventors: Gupta, Anil, Norman, Robert D., Lofgren, Karl M. J., Thelin, Gregory B.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/262,813
• Time in Patent Office: 480 Days
• Field of Search: 365/185.02, 365/185.09, 365/185.11, 365/185.28, 365/185.29, 365/185.22
• US Class Current: 365/185.02
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A mass storage system made of flash electrically erasable and programmable read only memory ("EEPROM") cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

Claims

1. A memory system, comprising:

an interface circuit for connection with a host computer system,

a buffer memory,

an array of flash EEPROM cells organized into non-overlapping blocks of cells that are erasable together as a unit prior to data being rewritten therein, said blocks of memory cells having an endurance limit of a maximum number of erase and rewrite cycles to which they can be subjected, ant

a control circuit managing movement of data between the interface circuit and the buffer memory, and between the buffer memory and the EEPROM array, including an address translator that receives an address of data received by the buffer memory from the host computer and changes a designation of an address of at least one block of the EEPROM array for storage of data in a manner that tends to even out the frequency of use of the EEPROM blocks prior to any of the individual blocks of memory cells reaching its endurance limit.

2. The memory system of claim 1, wherein the buffer memory is volatile.

3. The memory system of claim 1, wherein the control circuit operates to reference courts stored in the individual blocks of their frequency of use.

4. A memory system, comprising:

an interface circuit for connection with a host computer system,

a buffer memory,

an array of flash EEPROM cells organized into non-overlapping blocks of cells that are erasable together as a unit prior to data being rewritten therein, said blocks of memory cells having an endurance limit of a maximum number of erase and rewrite cycles to which they can be subjected, and

a control circuit managing movement of data between the interface circuit and the buffer memory, and between the buffer memory and the EEPROM array, including an address translator that receives an address of data received by the buffer memory from the host computer and, in response to the control circuit determining that the blocks have a predetermined unequal frequency of use, changes a designation of an address of at least one block of the EEPROM array for storage of data in a manner that tends to even out the frequency of use of the EEPROM blocks prior to any of the individual blocks of memory cells reaching its endurance limit.

5. The memory system of claim 4, wherein the buffer memory is volatile.

6. The memory system of claim 4, wherein the control circuit operates to reference counts stored in the individual blocks of their frequency of use when determining that the blocks have a predetermined unequal frequency of use.