Stress test mode entry at power up for low/zero power memories

• US 6,081,466 A
• Filed: 10/30/1998
• Issued: 06/27/2000
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: McClure, David C., Youssef, Tom
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/183,451
• Time in Patent Office: 606 Days
• Field of Search: 365/201, 365/226, 365/227
• US Class Current: 365/201
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously

Abstract

A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

Claims

1. A memory device, comprising:

a memory array for storing information, the memory array including operational circuits for controlling wordline and column activation;

means for placing the memory device into a deselect mode of operation wherein the operational circuits needed for wordline and column activation are disabled until an external pin application of a memory device supply voltage exceeds a first threshold; and

a test mode circuit for detecting test mode activation when a voltage appearing on a test pad of the memory device exceeds a second threshold and then overriding the deselect mode of operation to activate the wordline and column related operational circuits at memory device power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

2. The memory device as in claim 1 wherein the test mode circuit comprises:

a resistive element connected to the test pad;

a first logic circuit having an input connected to the test pad and having an output;

a second logic circuit having a first input connected to the output of the first logic circuit, a second input for receiving a mode signal relating to memory device mode of operation, and having and an output for generating a signal for overriding the deselect mode of operation.

3. The memory device as in claim 2 wherein the first logic circuit comprises a chain of inverters having an odd number of individual inverters.

4. The memory device of claim 2, wherein the second logic circuit includes a first logic gate.

5. The memory device as in claim 4 wherein the second logic circuit further includes a chain of inverters having an input connected to the output of the first logic gate and an output which generates the signal for overriding the deselect mode of operation.

6. The memory device as in claim 4, wherein the first logic gate comprises a NAND gate.

7. The memory device of claim 6, wherein the mode signal is applied to the second input of the NAND gate and identifies whether the memory device is in the sleep mode of operation.

8. The memory device as in claim 1, further including:

a means for placing the memory device in a sleep mode of operation powered by a back up battery when the external pin application of the memory device supply voltage falls below a third threshold.

9. The memory device as in claim 8, wherein the third threshold is less than the first threshold.

10. The memory device as in claim 1 wherein the second threshold is less than the first threshold.

11. A memory device, comprising:

a memory array for storing information, the memory array including operational circuits for controlling wordline and column activation;

a voltage sense and switching circuit responding to an external pin application of a memory device supply voltage below a first threshold with the generation of a mode control signal for disabling the operational circuits of the memory array needed for wordline and column activation; and

a test mode circuit responding to a test pad of the memory device having a voltage appearing thereon which is in excess of a second threshold, wherein the second threshold is less than the first threshold, with the generation of a signal for overriding the mode control signal output from the voltage sense and switching circuit and enabling the operational circuits of the memory array needed for wordline and column activation at memory device power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

12. The memory device of claim 11, wherein the test mode circuit comprises:

a first circuit having a first input coupled to the test pad, a second input for receiving a mode signal relating to the memory device mode of operation, and having an output which generates a signal for overriding the deselect mode of operation.

13. The memory device of claim 12, wherein the first circuit comprises:

a first logic gate having a first input coupled to the test pad, a second input for receiving a mode signal relating to the memory device mode of operation and an output; and

at least one second logic gate having an input connected to the output of the first logic gate and an output which generates the signal for overriding the deselect mode of operation.

14. The memory device of claim 13, wherein the at least one second logic gate comprises an inverter chain.

15. The memory device of claim 13, wherein the first logic gate comprises a NAND gate.

16. The memory device of claim 12, wherein the test mode circuit further comprises:

a second circuit having a first input connected to the test pad and an output connected to the input of the first circuit.

17. A method for memory device operation, comprising the steps of:

placing the memory device in a deselect mode of operation wherein certain operational circuits needed for wordline and column activation are disabled for so long as an external pin application of a memory device supply voltage is less than a first threshold;

detecting a voltage appearing on a test pad of the memory device being in excess of a second threshold, wherein the second threshold is less than the first threshold; and

responsive to an affirmative detection, overriding the placing of the memory device in the deselect mode of operation in order to activate the certain operational circuits at memory device power up such that the device powers up with multiple wordlines and columns activated.

18. The method as in claim 17 further including the step of applying a stress test overvoltage to the test pad and external pin.

19. The method of claim 17, further including the steps of:

ramping the voltage supply for the memory device from a substantially ground potential; and

ramping the voltage appearing on the test pad substantially concurrently with the step of ramping the voltage supply for the memory device.

20. The method of claim 17, further including the steps of:

generating a detection signal indicative of the voltage on the test pad being in excess of a second threshold during the step of detecting;

detecting a supply voltage for the memory device being in excess of the first threshold;

generating a mode signal indicative of the supply voltage for the memory device being in excess of the first threshold; and

the step of overriding includes the steps of gating the detection signal with the mode signal and generating a signal to activate the certain operational circuits at memory device power up.