Stress test mode entry at power up for low/zero power memories
First Claim
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1. A memory device, comprising:
- a memory array for storing information, the memory array including operational circuits for controlling wordline and column activation;
means for placing the memory device into a deselect mode of operation wherein the operational circuits needed for wordline and column activation are disabled until an external pin application of a memory device supply voltage exceeds a first threshold; and
a test mode circuit for detecting test mode activation when a voltage appearing on a test pad of the memory device exceeds a second threshold and then overriding the deselect mode of operation to activate the wordline and column related operational circuits at memory device power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.
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Abstract
A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.
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Citations
20 Claims
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1. A memory device, comprising:
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a memory array for storing information, the memory array including operational circuits for controlling wordline and column activation; means for placing the memory device into a deselect mode of operation wherein the operational circuits needed for wordline and column activation are disabled until an external pin application of a memory device supply voltage exceeds a first threshold; and a test mode circuit for detecting test mode activation when a voltage appearing on a test pad of the memory device exceeds a second threshold and then overriding the deselect mode of operation to activate the wordline and column related operational circuits at memory device power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory device, comprising:
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a memory array for storing information, the memory array including operational circuits for controlling wordline and column activation; a voltage sense and switching circuit responding to an external pin application of a memory device supply voltage below a first threshold with the generation of a mode control signal for disabling the operational circuits of the memory array needed for wordline and column activation; and a test mode circuit responding to a test pad of the memory device having a voltage appearing thereon which is in excess of a second threshold, wherein the second threshold is less than the first threshold, with the generation of a signal for overriding the mode control signal output from the voltage sense and switching circuit and enabling the operational circuits of the memory array needed for wordline and column activation at memory device power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method for memory device operation, comprising the steps of:
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placing the memory device in a deselect mode of operation wherein certain operational circuits needed for wordline and column activation are disabled for so long as an external pin application of a memory device supply voltage is less than a first threshold; detecting a voltage appearing on a test pad of the memory device being in excess of a second threshold, wherein the second threshold is less than the first threshold; and responsive to an affirmative detection, overriding the placing of the memory device in the deselect mode of operation in order to activate the certain operational circuits at memory device power up such that the device powers up with multiple wordlines and columns activated. - View Dependent Claims (18, 19, 20)
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Specification