Apparatus and method for shaping random waveforms

• US 6,081,858 A
• Filed: 11/26/1997
• Issued: 06/27/2000
• Est. Priority Date: 11/26/1997
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Abudayyeh, Jihad, Pathak, Sanjiv
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/979,188
• Time in Patent Office: 944 Days
• Field of Search: 710/102, 710/103, 327/91, 327/94, 327/109, 341/122, 388/901
• US Class Current: 710/301
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals

Abstract

A method and circuit to regulate a random waveform signal to ensure that the LED indicator driven by the waveform signal is visible to the human eye is provided. The method and circuit first determines whether there is a pulse occurring. If an on-going pulse is detected, the regulated waveform signal is driven HIGH for at least 8 clock cycles. If no on-going pulse is detected, the regulated waveform signal is driven LOW for at least 8 clock cycles.

Claims

1. A waveform signal regulating circuit comprising:

a sample-and-hold circuit receiving as input a transaction activity waveform signal;

a latch coupled to the sample-and-hold circuit, the latch generating a regulated waveform signal at an output;

wherein the sample-and-hold circuit detecting whether there is an on-going transaction activity, if there is an on-going transaction activity, the sample-and-hold detecting whether a pulse is occurring in the regulated waveform signal, if a pulse is not occurring in the regulated waveform signal, the sample-and-hold circuit signaling the latch to assert a first state in the regulated waveform signal for at least N clock cycles thereby controlling a pulse width, if there is no on-going transaction activity, the sample-and-hold circuit detecting whether a pulse is occurring in the regulated waveform signal, if a pulse is not occurring in the regulated waveform signal, the sample-and-hold circuit signaling the latch to assert a second state in the regulated waveform signal for at least M clock cycles thereby controlling a gap between two pulses;

wherein the sample-and-hold circuit comprises a first counter coupled to the latch, the first counter monitoring a first count in response to the regulated waveform signal, the first counter generating a signal having the first state while the first count is less than the value N, the first counter generating the signal having a second state when the first count reaches the value N;

a second counter coupled to the latch, the second counter monitoring a second count in response to a complementary of the regulated waveform signal, the second counter generating a signal having the first state while the second count is less than the value M, the second counter generating the signal having the second state when the second count reaches the value M; and

a switching circuit receiving as inputs the waveform signal and the signals generated by the first and second counters, the switching circuit outputting first and second output signals generated by the first and second counters, the first and second output signals from the switching circuit provided as inputs to the latch;

wherein the first and second counters start the first and second counts when the regulated waveform signal and the complementary of the regulated waveform signal are HIGH, the first and second counters reset the first and second counts when the regulated waveform signal and the complementary of the regulated waveform signal are LOW; and

wherein the switching circuit comprises an AND-gate receiving as inputs the waveform signal and an invert of the signal generated by the second counter, the AND-gate providing as output the first output signal of the switching circuit; and

a NOR-gate receiving as inputs the waveform signal and the signal generated by the first counter, the NOR-gate providing as output the second output signal of the switching circuit.

2. The waveform signal regulating circuit of claim 1, wherein the AND-gate further receiving as an input the invert of an enable signal which is asserted LOW in activating the waveform signal regulating circuit.

3. The waveform signal regulating circuit of claim 1, wherein the latch is a RS-type latch, the RS-type latch receiving the first output signal of the switching circuit at a S input, the RS-type latch receiving the second output signal of the switching circuit at a R input.

4. The waveform signal regulating circuit of claim 1, wherein the values N and M are equal to eight (8).

5. A computer system comprising:

a host processor;

a system memory;

a PC card host adaptor; and

a system bus coupling together the host processor, the system memory, and the PC card host adaptor;

wherein the PC card host adapter comprises a waveform signal regulating circuit comprising;

a sample-and-hold circuit receiving as input a transaction activity waveform signal;

a latch coupled to the sample-and-hold circuit, the latch generating a regulated waveform signal at an output;

wherein the sample-and-hold circuit detecting whether there is an on-going transaction activity, if there is an on-going transaction activity, the sample-and-hold detecting whether a pulse is occurring in the regulated waveform signal, if a pulse is not occurring in the regulated waveform signal, the sample-and-hold circuit signaling the latch to assert a first state in the regulated waveform signal for at least N clock cycles thereby controlling a pulse width, if there is no on-going transaction activity, the sample-and-hold circuit detecting whether a pulse is occurring in the regulated waveform signal, if a pulse is not occurring in the regulated waveform signal, the sample-and-hold circuit signaling the latch to assert a second state in the regulated waveform signal for at least M clock cycles thereby controlling a gap between two pulses;

wherein the sample-and-hold circuit comprises a first counter coupled to the latch, the first counter monitoring a first count in response to the regulated waveform signal, the first counter generating a signal having the first state while the first count is less than the value N, the first counter generating the signal having a second state when the first count reaches the value N;

a second counter coupled to the latch, the second counter monitoring a second count in response to a complementary of the regulated waveform signal, the second counter generating a signal having the first state while the second count is less than the value M, the second counter generating the signal having the second state when the second count reaches the value M; and

a switching circuit receiving as inputs the waveform signal and the signals generated by the first and second counters, the switching circuit outputting first and second output signals generated by the first and second counters, the first and second output signals from the switching circuit provided as inputs to the latch;

wherein the first and second counters start the first and second counts when the regulated waveform signal and the complementary of the regulated waveform signal are HIGH, the first and second counters reset the first and second counts when the regulated waveform signal and the complementary of the regulated waveform signal are LOW; and

wherein the switching circuit comprises an AND-gate receiving as inputs the waveform signal and an invert of the signal generated by the second counter, the AND-gate providing as output the first output signal of the switching circuit; and

a NOR-gate receiving as inputs the waveform signal and the signal generated by the first counter, the NOR-gate providing as output the second output signal of the switching circuit.

6. The computer system of claim 5, wherein the AND-gate further receiving as an input the invert of an enable signal which is asserted LOW in activating the waveform signal regulating circuit.

7. The computer system of claim 5, wherein the latch is a RS-type latch, the RS-type latch receiving the first output signal of the switching circuit at a S input, the RS-type latch receiving the second output signal of the switching circuit at a R input.

8. The computer system of claim 5, wherein the values N and M are equal to eight (8).

9. An apparatus for shaping random waveforms, comprising:

first and second counters individually reset each time after counting to a corresponding predetermined count; and

a sample-and-hold having an input receiving a random waveform and an output providing a shaped waveform useful for driving a visible indicator indicating transaction activity on said random waveform, and coupled to said first and said second counters such that said shaped waveform is generated by sampling said random waveform each time one of said first and said second counters is reset and held while counting to said corresponding predetermined count;

wherein said first counter is coupled to said sample-and-hold so as to count to a first predetermined count if said random waveform is at a first logic level when sampled, and said second counter is coupled to said sample-and-hold so as to count to a second predetermined count if said random waveform is at a second logic level when sampled; and

said sample-and-hold includes a latch having an output, and coupled to said first counter so as to initiate said first counter counting when said latch output is in a first logic state, and coupled to said second counter so as to initiate said second counter counting when said latch output is in a second logic state; and

logic having an input receiving said random waveform, and coupled to said latch, said first counter, and said second counter such that said logic causes said latch output to be in said first logic state when said random waveform is at said first logic level when sampled, and said logic causes said latch output to be in said second logic state when said random waveform is at said second logic level when sampled.

10. The apparatus according to claim 9, wherein said logic comprises:

AND logic having a first input coupled to said random waveform, and a second input coupled to an inverted output of said second counter, wherein said output of said second counter indicates when said second counter is reset; and

NOR logic having a first input coupled to said random waveform, and a second input coupled to an output of said first counter, wherein said output of said first counter indicates when said first counter is reset.

11. The apparatus according to claim 10, wherein said latch comprises an S-R latch having an S-input coupled to an output of said AND logic, an R-input coupled to an output of said NOR logic, a Q-output coupled to an enable input of said first counter, and a Q-bar-input coupled to an enable input of said second counter.

12. A method for shaping random waveforms, comprising:

(a) detecting transaction activity on a random waveform;

(b) if transaction activity is detected on said random waveform, generating a shaped waveform by holding said shaped waveform at a first logic level for a first predetermined count, then repeating steps (a) through (c); and

(c) if transaction activity is not detected on said random waveform, generating said shaped waveform by holding said shaped waveform at a second logic level for a second predetermined count, then repeating steps (a) through (c).

13. The method according to claim 12, wherein (b) comprises:

if transaction activity is detected on said random waveform, enabling said first counter to count to a first predetermined count while holding a shaped waveform at a first logic level, then repeating steps (a) through (c) after counting to said first predetermined count.

14. The method according to claim 12, wherein (c) comprises:

if transaction activity is not detected on said random waveform, enabling a second counter to count to a second predetermined count while holding said shaped waveform at a second logic level, then repeating steps (a) through (c) after counting to said second predetermined count.

15. The method according to step 12, wherein a period in which said shaped waveform is at said first logic level directly correlates to a duration of said transaction activity.

16. The method according to step 12, wherein an interval between successive periods in which said shaped waveform is at said first logic level directly correlates to a time interval between successive transaction activities.