Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

• US 6,081,878 A
• Filed: 02/25/1998
• Issued: 06/27/2000
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro, Iman, Berhanu
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): McLean, Kimberly
• Application Number:
  US09/030,697
• Time in Patent Office: 853 Days
• Field of Search: 711/103, 711/112, 711/114, 711/5, 711/168, 711/202, 711/150, 365/185.11, 365/230.03, 365/230.06, 365/185.13
• US Class Current: 711/168
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

The present invention includes a digital system having a controller semiconductor device coupled to a host and a nonvolatile memory bank including a plurality of nonvolatile memory devices. The controller transfers information, organized in sectors, with each sector including a user data portion and an overhead portion, between the host and the nonvolatile memory bank and stores and reads two bytes of information relating to the same sector simultaneously within two nonvolatile memory devices. Each nonvolatile memory device is defined by a row of memory locations wherein corresponding rows of at least two semiconductor devices maintain two sectors of information therein with the overhead information relating to the two sectors maintained in one of the memory rows of the nonvolatile memory device. Each 32 sectors of information defines a block identified by a virtual physical block address with a block of information expanding between two memory devices wherein an even and an odd byte of a sector is simultaneously read from or written to two nonvolatile memory devices. In another embodiment, the controller stores an entire sector of information within a single nonvolatile memory device and reads from or writes to, a sector of information by processing corresponding bytes of at least two sectors in two nonvolatile memory devices simultaneously.

Claims

1. A memory storage system for storing information organized in sectors within a nonvolatile memory bank defined by sector store locations spanning across two or more nonvolatile memory devices, each said sector including a user data portion and an overhead portion, said sectors being organized into blocks, each sector identified by a host provided logical block address (LBA) and an actual physical block address (PBA) derived from a virtual PBA, each block being identified by a modified LBA derived from said host-provided LBA and said virtual PBA, said host-provided LBA being received by said storage system from the host for identifying a sector of information to be accessed, said actual PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed sector is to be stored, said storage system comprising:

a memory controller coupled to said host; and

a nonvolatile memory bank coupled to said memory controller via a memory bus, said memory bank including a first non-volatile semiconductor memory unit and a second non-volatile semiconductor memory unit, said memory bank having storage blocks each of which includes at least one memory row location having a first row-portion located in said first memory unit, and a corresponding second row-portion located in said second memory unit, each said memory row location providing storage space for two of said sectors,

wherein the speed of performing write operations is increased by writing sector information to two or more nonvolatile memory devices simultaneously.

2. A memory storage system as recited in claim 1 wherein said memory controller includes:

a data buffer for temporarily storing said sector-organized information;

a microprocessor;

a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating said LBA to said PBA; and

an error correction code logic unit for performing error coding and correction operations on said sector-organized information.

3. A memory storage system as recited in claim 1 wherein:

each of said first row-portions includes,

a first even sector field for storing even data bytes of an even sector, and

a first odd sector field for storing even data bytes of an odd sector;

each of said second row-portions includes,

a second even sector field for storing odd data bytes of said even sector, and

a second odd sector field for storing odd data bytes of said odd sector;

said memory bus includes,

a first split bus coupled to transmit said even data bytes of said sectors between said memory controller and said first memory unit;

a second split bus coupled to transmit said odd data bytes of said sectors between said memory controller and said second memory unit.

4. A memory storage system as recited in claim 3 wherein each of said second row-portions further includes:

a first error correction field for storing error correction information corresponding to said even sector;

a second error correction field for storing error correction information corresponding to said odd sector;

a block address field for storing said PBA which specifies an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

5. A memory storage device as recited in claim 4 wherein each of said first row-portions further includes:

a first error correction field for storing error correction information corresponding to said even sector;

a second error correction field for storing error correction information corresponding to said odd sector; and

a block address field for storing said PBA which specifies an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

6. A memory storage system as recited in claim 5 wherein:

each of said first and second row-portions includes storage space for 512 bytes of said user data plus an additional 16 bytes of storage space for said overhead information; and

said first split bus and said second split bus each include 8 bit lines.

7. A memory storage system as recited in claim 6 wherein said controller includes:

means for accessing an even sector of information by simultaneously accessing said first and second even sector fields of corresponding row-portions of said first and second memory units via said first and second split buses; and

means for accessing an odd sector of information by simultaneously accessing said first and second odd sector fields of corresponding row-portions of said first and second memory units via said first and second split buses.

8. A memory storage system as recited in claim 7 wherein said controller includes error correction code logic for performing error coding and correction operations on said sector-organized information.

9. A memory storage system as recited in claim 8 wherein said flag field is used to store block level flags including:

a used/free block flag indicating whether said corresponding block is currently being used to store information; and

a defect block flag indicating whether said corresponding block is defective.

10. A memory storage system as recited in claim 9 wherein each of said corresponding sub-blocks are identified by a single PBA value.

11. A memory storage system as recited in claim 10 wherein said non-volatile memory units are flash memory chips.

12. A memory storage system as recited in claim 11 wherein:

each of said first row-portions includes a first sector field for storing data bytes of a first sector;

each of said second row-portions includes a second sector field for storing data bytes of a second sector;

said memory bus includes,

a first split bus coupled to transmit (least significant ?) data bytes of said sectors between said memory controller and said first memory unit;

a second split bus coupled to transmit (most significant ?) data bytes of said sectors between said memory controller and said second memory unit.

13. A memory storage system as recited in claim 12 wherein:

means for simultaneously accessing said first and second sector fields of corresponding row-portions of said first and second memory units via said first and second split buses.

14. In a storage system including a non-volatile memory bank and a controller coupled to said memory bank via a memory bus, said memory bank including a first non-volatile memory unit and a second non-volatile memory unit, said memory bank having storage locations defined by blocks, each block for storing a plurality of sectors of information, each sector having a user data portion and an overhead portion, each block including at least one memory row location having a first row-portion located in said first memory unit, and a corresponding second row-portion located in said second memory unit, a process of writing a first sector and a second sector to said memory bank during a single write operation, said process including the steps of:

simultaneously transmitting a write command to said first and second memory units;

addressing one of said memory row locations of said memory bank by simultaneously addressing corresponding first and second row portions of said addressed row location;

transmitting a first data byte of said first sector to said first memory unit while simultaneously transmitting a second data byte of said first sector to said second memory unit and after transmission of all of the bytes of the first sector to the first and second memory units, transmitting the first byte of said second sector to said first memory unit while simultaneously transmitting a second byte of said second sector to said second memory unit,

wherein two sectors of information are stored in one memory row location of said memory bank by simultaneously transmitting two byte of sector information thereby increasing the speed of write operations of the storage system.

15. In a storage system including a memory bank and a controller as recited in claim 14 wherein an even sector and an odd sector are stored in a single memory row location and wherein even user data bytes of said first and second sectors are stored in said first memory unit and odd user data bytes of said first and second sectors are stored in said second memory unit and wherein overhead information associated with said first and second sectors is stored in one of said first and second row portions.

16. In a storage system including a memory bank and a controller as recited in claim 15 wherein a block address entry is entered in a block address field in a last row location of each said block.

17. In a storage system including a memory bank and a controller as recited in claim 16 wherein said controller accesses an even sector of information stored collectively in said first and second flash memory chips by simultaneously accessing first and second even sector fields of corresponding row-portions of said first and second flash memory chips via said first and second split buses

said first and second split buses including lines coupled to receive said even and odd data bytes respectively of a sector of information

said controller accesses an odd sector of information stored collectively in said first and second flash memory chips by simultaneously accessing said first and second odd sector fields, via said first and second split buses

said split buses also providing for transmission of ECC information between said flash memory chips and said flash state machine and ECC logic unit of said memory controller;

and transmission of address information from flash state machine to said flash memory chips.

18. In a storage system including a memory bank and a controller as recited in claim 17 wherein said flag field is used to store block level flags including:

a used/free block flag indicating whether said corresponding block is currently being used to store information

a defect block flag indicating whether said corresponding block is defective.

19. In a storage system including a memory bank and a controller as recited in claim 18, each block having associated therewith a modified logical block address (LBA) derived from a host-provided LBA value and an actual physical block address (PBA) derived from a virtual PBA value, said host-provided LBA value received by said controller from the host for identifying a sector of information to be accessed, said actual PBA developed by said storage system for identifying a free location within said memory bank wherein a sector of information identified by the host is to be stored, wherein each of said corresponding sub-blocks are identified by a single virtual PBA value.

20. In a storage system including a nonvolatile memory bank and a controller coupled to said memory bank via a memory bus, said memory bank including a first non-volatile memory unit and a second non-volatile memory unit, said memory bank having storage blocks for storing information sectors each of which includes a user data portion and an overhead portion, each block having associated therewith a logical block address (LBA) and a physical block address (PBA), said LBA provided by a host to said controller for identifying a block to be accessed, said PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed block is to be stored, each block including at least one memory row location having a first row-portion located in said first memory unit, and a corresponding second row-portion located in said second memory unit, a process of writing a first sector and a second sector to said memory bank during a single write operation, said process including the steps of:

simultaneously providing a write command to said first and second memory units;

addressing one of said memory row locations of said memory bank by simultaneously addressing corresponding first and second row portions of said addressed row location;

storing even data bytes of an even sector to a first even sector field of said addressed first row-portion;

storing even data bytes of an odd sector to a first odd sector field of said first addressed row-portion;

storing odd data bytes of said even sector to a second even sector field of said second addressed row-portion; and

storing odd data bytes of said odd sector of information to a second odd sector field of said second addressed row-portion.

21. In a storage device including a memory bank and a controller as recited in claim 20 further including the steps of:

determining even sector error correction information corresponding to said even sector of information and odd sector error correction information corresponding to said odd sector of information;

storing said even sector error correction information to a first error correction field of said second addressed row-portion; and

storing said odd sector error correction information to a second error correction field of said second addressed row-portion.

22. In a storage device including a nonvolatile memory bank and a controller coupled to said memory bank via a memory bus, said memory bank including a first non-volatile memory unit and a second non-volatile memory unit, said memory bank having blocks for storing sectors of information each of which includes a user data portion and an overhead portion, each said block having associated therewith a logical block address (LBA) and a physical block address (PBA), said LBA provided by a host to said controller for identifying a sector of information to be accessed, said PBA developed by said storage system for identifying a free block location within said memory bank wherein said accessed block is to be stored, each block including at least one memory row location having a first row-portion located in said first memory unit, and a corresponding second row-portion located in said second memory unit, said controller including a data buffer;

a process of writing sector-organized information to said memory bank, said process including the steps of;

receiving host-provided LBA values from said host, each said host-provided LBA value for identifying a sector of information;

modifying a current host-provided LBA to identify a block of sectors of information;

providing a map having map row locations identified by said modified LBA values or virtual PBA values, said map used as a look-up-table for storing virtual PBA values corresponding to modified LBA values;

setting a sector count value equal to the number of sectors of information identified by the host;

searching for a free block within said memory bank identified by a current virtual PBA;

storing said current virtual PBA, corresponding to said free block, in a map row location identified by said modified current LBA in said map;

determining whether said current host-provided LBA is even and whether said sector count is greater than one;

if said current actual PBA value is even and said sector count is greater than one,

simultaneously writing two sectors of information, one sector identified by said current host-provided LBA and a second sector of information identified by said current host-provided LBA plus one, said first sector being written to said first non-volatile memory unit and said second sector being written to said second non-volatile memory units of said memory bank,

decrementing said sector count by two,

determining whether said sector count is equal to zero,

if said sector count is not equal to zero, increasing said current host-provided LBA value by two to point to the next sector that is to be written,

if said current host-provided LBA value or said sector count is not greater than one,

simultaneously writing even data bytes of a current sector of information identified by said current host-provided LBA to said first non-volatile memory unit and odd data bytes of said current sector to said second non-volatile memory unit,

decrementing said sector count by one,

determining whether said sector count is equal to zero, and

if said sector count is not equal to zero, increasing said current host-provided LBA by one to point to the next sector of information that is to be written.

23. In a storage device including a memory bank and a controller as recited in claim 22, wherein said step of simultaneously writing said two current sectors to said first and second non-volatile memory units of said memory bank, includes the steps of:

simultaneously providing a write command to said first and second memory units;

addressing one of said memory row locations of said memory bank by simultaneously addressing corresponding first and second row portions of said addressed row location;

storing even data bytes of an even sector to a first even sector field of said first addressed row-portion;

storing even data bytes of an odd sector to a first odd sector field of said first addressed row-portion;

storing odd data bytes of said even sector to a second even sector field of said second addressed row-portion; and

storing odd data bytes of said odd sector of information to a second odd sector field of said second addressed row-portion.

24. In a storage device including a memory bank and a controller as recited in claim 23, further including the steps of:

determining whether or not each of said addressed sector locations of a current block has been accessed since the last erasure thereof by reading the contents of the corresponding virtual PBA field of the LBA-PBA map;

setting a move flag corresponding to said current block if said current block has been accessed since the last erasure thereof;

subsequent to performing a write operation

determining whether said move flag is set;

if said move flag is set, updating said current block by moving those of said sectors not written to which belong to said current block to corresponding sector locations in said free block.