Method of resetting a system

• US 6,081,889 A
• Filed: 06/19/1998
• Issued: 06/27/2000
• Est. Priority Date: 06/25/1997
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kitao, Ichiro
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/100,817
• Time in Patent Office: 739 Days
• Field of Search: 713/1, 713/500, 713/100
• US Class Current: 713/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges

Abstract

A method of resetting a system enables an EEPROM writing to be implemented to the end normally, and it is capable of avoiding runaway of the whole system, even if reset signal is received because of a power failure while the EEPROM is in the writing state. In the system which has a CPU, an EEPROM whole circuit, an oscillation circuit, and a reset control circuit, when a system reset occurs, the method includes detecting a writing operation of the EEPROM cell, in cases where the EEPROM cell is implementing the writing operation, holding the reset of the EEPROM cell until the writing operation of the EEPROM cell is terminated, thus implementing the reset of at least the CPU.

Claims

1. A method of resetting a system including a CPU, a storing device, an oscillation circuit and a reset control. circuit, said resetting method comprising the steps of:

detecting a writing operation of said storing device at the time when a system reset signal occurs by means of said reset control circuit; and

holding a reset of said storing device until the writing operation of said storing device is terminated when said storing device is implementing the writing operation at the time a reset signal is received, while implementing at least a reset of said CPU.

2. A method of resetting a system as claimed in claim 1, wherein said storing device includes an EEPROM (electrically erasable programmable read-only memory).

3. A method of resetting a system as claimed in claim 1, wherein there is implemented a detection of the writing operation of said storing device by a status circuit of said storing device.

4. A method of resetting a system as claimed in claim 1, wherein there is implemented continuation of the writing operation of said storing device by either a ring oscillator or an oscillation circuit.

5. A method of resetting a system including a CPU, a storing device, an oscillation circuit and a reset control circuit, said resetting method comprising the steps of:

detecting a writing operation of said storing device at the time when a system reset signal occurs by means of said reset control circuit; and

holding a reset of said storing device and said oscillation circuit until the writing operation of said storing device is terminated when said storing device is implementing the writing operation, at the time a reset signal is received, while implementing at least a reset of said CPU.