Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon

• US 6,083,846 A
• Filed: 04/24/1998
• Issued: 07/04/2000
• Est. Priority Date: 01/10/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., Fulford, H. Jim Jr., Hause, Fred N.
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US09/065,508
• Time in Patent Office: 802 Days
• Field of Search: 438/305, 438/306, 438/595, 438/696, 438/719, 438/738, 438/740, 438/753
• US Class Current: 438/740
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a lateral surface to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. Preferably, the multi-layer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The oxide is grown upon the polysilicon to align a source/drain implant. Either before the source/drain implant or after the source/drain implant, the oxide and polysilicon partially consumed by the oxide is removed to provide a lateral surface to which an MDD implant aligns. A combination of etch stop, polysilicon spacer and grown possibly sacrificial oxide allows a greater ease by which multiple implants can be forwarded into junctions of either an NMOS or PMOS transistor.

Claims

1. A method for forming a transistor, comprising:

providing a semiconductor substrate over which a gate conductor having opposed sidewall surfaces is dielectrically spaced; and

depositing an etch stop layer upon the sidewall surfaces, followed by depositing a polysilicon spacer upon the etch stop layer and followed by growing an oxide upon the polysilicon spacer to form a multi-layer spacer.

2. The method as recited in claim 1, wherein said multi-layer spacer serves as a mask to which a sequence of implants are successively aligned after formation of said sidewall surfaces, followed by formation of said etch stop, followed by formation of said polysilicon spacer and followed by formation of said oxide.

3. The method as recited in claim 1, wherein said multi-layer spacer serves as a mask to which a sequence of implants are successively aligned after removal of said oxide, after removal of said polysilicon spacer and after removal of said etch stop.

4. The method as recited in claim 1, wherein one of a plurality of implants is forwarded into junction regions within said semiconductor substrate laterally defined between the polysilicon spacer removed of said oxide.

5. The method as recited in claim 1, further comprising implanting dopants of differing concentrations into a pair of junction areas between which a channel area is interposed, said dopants are implanted in succession after a respective said etch stop, said polysilicon spacer and said oxide is formed.

6. The method as recited in claim 1, further comprising implanting dopants of differing concentrations into a pair of junction areas between which a channel area is interposed, said dopants are implanted in succession after a respective said etch stop, said polysilicon spacer and said oxide is removed.

7. The method as recited in claim 1, wherein said etch stop, said polysilicon spacer and said oxide have dissimilar etch characteristics corresponding to selectively removal thereof.

8. A method for forming an integrated circuit, comprising:

providing a semiconductor topography upon which a gate conductor having opposed sidewall surfaces is formed;

forming a sequence of dielectric layers upon the sidewall surfaces, wherein one of said sequence of dielectric layers comprises a grown oxide which, during thermal growth, partially consumes an immediately underlying, silicon-based dielectric layer,

implanting into a junction area within said semiconductor topography after said sequence of dielectric layers is at least partially formed; and

implanting into the junction area after said oxide and the partially consumed underlying silicon-based dielectric layer are removed.

9. The method as recited in claim 8, wherein said first implanting step occurs at a concentration and implant energy dissimilar from said second implanting step.

10. The method as recited in claim 8, wherein said sequence of dielectric layers comprises a polysilicon spacer interposed between an etch stop layer and an oxide layer, the etch stop layer being immediately adjacent said sidewall surfaces and comprises a layer of silicon dioxide and a layer of silicon nitride.

11. The method as recited in claim 8, wherein said layer of silicon dioxide is thermally grown upon and within said sidewall surfaces and said layer of nitride is deposited upon said layer of silicon dioxide.