Front contact trenches for polycrystalline photovoltaic devices and semi-conductor devices with buried contacts

• US 6,084,175 A
• Filed: 11/14/1995
• Issued: 07/04/2000
• Est. Priority Date: 05/20/1993
• Status: Expired due to Term

• Current Assignee: BP Solar International Incorporated (BP PLC)
• Original Assignee: Amoco/Enron Solar Co.
• Inventors: Wohlgemuth, John H., Perry, James M., Narayanan, Srinvasamohan, Roncin, Steven P.
• Primary Examiner(s): Weisstuch, Aaron
• Application Number:
  US08/557,286
• Time in Patent Office: 1,694 Days
• Field of Search: 136/256, 257/436, 257/466, 437/2, 437/4-5, 437/203
• US Class Current: 136/256
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/02363 of the semiconductor body itself, e.g. textured active layers
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Textured semi-conductor devices, such as macro textured buried-contact solar cells, are produced with special front contact trenches to increase efficiency and decrease costs. In order to produce the front contact trenches, front channels and narrower metallization grooves are cut in the semi-conductor body. The front contact trenches are plated to form attractive conductive buried contacts comprising flush metallization fingers and bus bars.

Claims

1. A semi-conductor device, comprising:

a semi-conductor body having a textured surface defining an array of peaks and valleys;

a channel disposed in said textured surface and extending through a multitude of said peaks to a depth in proximity to said valleys;

a groove extending below said channel beneath said textured surface and said groove having a width narrower than said channel;

a metal conductive layer positioned in said groove; and

said metal conductive layer and said groove cooperating with each other to form a conductive buried contact substantially in the absence of zig-zag metallization of varying depths in said groove and channel.

2. A semi-conductor device in accordance with claim 1 including insulation disposed in said channel to insulate said channel from said conductive buried contact.

3. A semi-conductor device in accordance with claim 1 wherein:

said semi-conductor body has an edge in the absence of metal, said edge providing a border peripherally surrounding said groove, said edge defines an isolation trench, and said isolation trench has a depth greater than said channel and groove;

insulating material disposed in and substantially covering said isolation trench to substantially prevent metal from contacting said edge and shunting said semi-conductor device; and

said isolation trench and said insulating material cooperating with each other to isolate and insulate the edge of the semi-conductor device from said conductive buried contact.

4. A semi-conductor device in accordance with claim 3 wherein:

said channel comprises an etched sawed channel;

said groove comprise an etched sawed groove;

said isolation trench comprises an etched sawed trench; and

said metal conductive layer is selected from the group consisting of nickel, copper, silver, and combinations thereof.

5. A semi-conductor device in accordance with claim 3 including a diffused layer providing opposite conductivity regions beneath said isolation trench, channel, and groove.

6. A semi-conductor device in accordance with claim 1 wherein said textured surface comprises a textured portion selected from the group consisting of pyramids, macro-grooves, V-shaped grooves, rounded peaks, pointed apexes, and combinations thereof.

7. A semi-conductor device in accordance with claim 1 comprising a photovoltaic device or solar cell.

8. A photovoltaic device, comprising:

a silicon wafer selected from the group consisting of a polycrystalline wafer and a monocrystalline wafer, said silicon wafer providing a solar cell, said silicon wafer having a textured surface for decreasing reflection of light and increasing photovoltaic efficiency, and said textured surface having apexes and a base;

said silicon wafer defining a substantially parallel set of channels providing front contact trenches extending substantially across said textured surface for enhancing trapping of light, said front contact trenches extending through a substantial amount of said apexes to a depth adjacent said base of said textured surface;

insulation positioned within and substantially engaging and covering said front contact trenches to substantially prevent metal from contacting said front contact trenches so as to minimize shadowing, said insulation comprising at least one insulating material selected from the group consisting of silicon oxide, silicon nitride, and oxided materials;

said silicon wafer defining a set of metallization grooves aligned in registration with and extending below said front contact trenches, said grooves extending beneath said base of said textured surface and spanning a width less than said front contact trenches, and said metallization grooves comprising metallization finger grooves and bus bar grooves;

metal conductive plating substantially filling said metallization grooves, and providing metal conductive layers selected from the group consisting of nickel, copper, silver, and combinations thereof, and said metal conductive layers comprising metallization fingers and bus bars;

said metallization grooves and said metal conductive layers cooperating with each other to form conductive buried contacts positioned substantially below the base of said textured surface, said conductive buried contacts having a substantially uniform depth below said front contact trenches and being substantially coplanar; and

said front contact trenches and said conductive buried contacts cooperating with each other to enhance the open circuit voltage of said photovoltaic device.

9. A photovoltaic device in accordance with claim 8 wherein:

said textured surface defines substantially parallel V-shaped texturing grooves;

said metallization fingers, metallization finger grooves, and front contact trenches for said metallization fingers are positioned transverse to said V-shaped texturing grooves; and

said bus bar, bus bar grooves, and front contact trenches for said bus bar are positioned substantially parallel to said V-shaped texturing grooves.

10. A photovoltaic device in accordance with claim 8 wherein:

said front contact trenches define etched sawed front contact trenches formed by a dicing saw and subsequent etching;

said metallization grooves define etched sawed grooves formed by a dicing saw and subsequent etching;

said wafer has an edge in the absence of metal, said edge providing a border peripherally surrounding said grooves, said edge defining an isolation trench, and said isolation trench being deeper than said front contact trenches and said grooves;

insulating material positioned within and substantially engaging and covering said isolation trench to substantially prevent metal from contacting said edge and shorting said solar cell, said insulating material comprising at least one insulating material selected from the group consisting of silicon oxide, silicon nitride, and oxided materials; and

said isolation trench and said insulating material cooperate with each other to isolate and insulate the edge of the solar cell from said conductive buried contacts.

11. A photovoltaic device in accordance with claim 10 including a phosphorous silicon diffused layer providing

N⁺ regions beneath said isolation trench and said front contact trenches, and

N⁺⁺ regions beneath said metallization grooves;

and wherein

said isolation trench comprises an etched sawed isolation trench formed by a dicing saw and subsequent etching.

12. A photovoltaic device in accordance with claim 10 wherein:

said front contact trenches for said metallization fingers have a width of about 30-150 microns and a depth of about 30-90 microns;

said metallization finger grooves have a depth from about 30-70 mm below said front contact trenches for said metallization fingers;

said front contact trenches for said bus bars have a width of about 1.8-2 microns and a depth of about 30-90 microns;

said bus bar grooves have a depth of 30-70 microns below said front contact trenches for said bus bar, and about 44-60 bus bar grooves are associated with each bus bar.

13. A photovoltaic device in accordance with claim 12 wherein said isolation trench has a depth of about 50-100 microns and a width of about 40-100 microns.

14. A process for producing a photovoltaic device, comprising the steps of:

preparing a silicon wafer selected from the group consisting of a P type polycrystalline wafer, a P type monocrystalline wafer, an N type polycrystalline wafer, and an N type monocrystalline wafer, into an array of solar cells with an enhanced efficiency by

macro-texturing said silicon wafer to form a macro-textured surface having apexes providing peaks and valleys along a base to reduce reflection of incoming light;

forming channels providing front contact trenches through a multitude of said apexes to enhance trapping of light, said channels being cut from said peaks to a depth in proximity to said valleys;

forming an emitter and a photovoltaic junction in said wafer by diffusing opposite type polarity regions in said silicon wafer including an active region and an area beneath said front contact trenches, said opposite type polarity regions being selected from the group consisting of an N⁺ region for a P type polycrystalline wafer, an N⁺ region for a P type monocrystalline wafer, a P⁺ region for an N type polycrystalline wafer, and a P⁺ region for an N type monocrystalline wafer;

insulating said front contact trenches with at least one insulating material selected from the group consisting of silicon oxide, silicon nitride, and oxided materials, to substantially prevent shadowing and metallization of said front contact trenches;

cutting metallization grooves in said silicon wafer having a width less than said channels, said grooves being aligned and cut through said front contact trenches to a depth substantially below said valleys and base of said macro-textured surface;

diffusing another opposite type polarity region in said silicon wafer beneath said metallization grooves, said another opposite polarity region being selected from the group consisting of an N⁺⁺ region for a P type polycrystalline wafer, an N⁺⁺ region for a P type monocrystalline wafer, a P⁺⁺ region for an N type polycrystalline wafer; and

a P⁺⁺ region for an N type monocrystalline wafer;

forming conductive buried contacts having a substantially uniform depth by plating and substantially filling said grooves with a metal conductive layer selected from the group consisting of nickel, copper, silver, and combinations thereof;

substantially preventing zig-zag metallization of varying depths in said groove and said front contact trenches.

15. A process for producing a photovoltaic device in accordance with claim 14 wherein:

said forming of said channels to provide said front contact trenches comprises a cutting procedure selected from the group selected consisting of laser cutting, sawing, scribing, screen printing, photolithography, chemical etching, plasma etching, and electron beam cutting;

said macro-textured surface comprises a macro-textured portion selected from the group consisting of pyramids, macro-grooves, V-shaped grooves, slots, concave peaks, convex valleys, pointed apexes, and combinations thereof;

said macro-texturing comprises a macro-textured procedure selected from the group consisting of pyramid texturing, chemical etching, laser cutting and sawing; and

said sawing includes etching to reduce saw damage.

16. A process for producing a photovoltaic device in accordance with claim 14 wherein:

said forming of said channels comprises sawing front contact trenches substantially across said wafer with a dicing saw and etching said front contact trenches to remove saw damage; and

said cutting of said metallization grooves comprises sawing metallization grooves substantially across said wafer with a dicing saw and etching said grooves to remove saw damage and enhance metallization.

17. A process for producing a photovoltaic device in accordance with claim 14 including substantially preventing shunting of said conductive buried contacts by:

cutting isolation trenches into said silicon wafer before cutting said channels providing said front contact trenches, and said isolation trenches being cut to a depth greater than the combined depths of said front contact trenches and grooves;

diffusing further opposite type polarity regions in said wafer beneath said isolated trenches concurrently with said diffusing of said opposite type polarity regions beneath said front contact trenches, said further opposite type polarity region being selected from the group consisting of an N⁺ region for a P type polycrystalline wafer, an N⁺ region for a P type monocrystalline wafer, a P⁺ region for an N type polycrystalline wafer; and

a P⁺ region for an N type monocrystalline wafer;

forming an edge in the absence of metal with said isolation trenches to provide a border for said solar cells, said border being located at a position on said silicon wafer to peripherally surround and be spaced from said conductive buried contacts and grooves;

substantially preventing metal from contacting said edge and shorting said conductive buried contacts by depositing and substantially covering said isolation trenches with insulation comprising at least one insulating material selected from the group consisting of silicon oxide, silicon nitride, and oxided materials, to provide an insulation barrier isolating and insulating said conductive buried contacts so as to enhance the efficiency of said solar cells; and

cutting through said isolation trenches to separate said solar cells.

18. A process for producing a photovoltaic device in accordance with claim 17 wherein:

said macro-texturing comprises;

sawing said silicon wafer with a dicing saw to from a substantially parallel set of V-shaped grooves peripherally surrounded by said isolation trenches, and

etching said V-shaped grooves to reduce saw damage; and

said cutting of said isolation trenches comprises

sawing said isolation trenches in said wafer with a dicing saw, and

etching said isolation trenches to reduce saw damage in said isolation trenches.

19. A process for producing a photovoltaic device in accordance with claim 17 wherein:

said front contact trenches are sawed to a depth of about 30-90 microns;

said metallization grooves are sawed to a depth of about 30-70 microns below said front contact trenches at of width of 10-100 microns; and

said isolation trenches are cut with a dicing saw to a depth of about 50-100 microns at a width of about 40-100 microns.