Power MOSFET device having low on-resistance and method

• US 6,084,268 A
• Filed: 11/03/1997
• Issued: 07/04/2000
• Est. Priority Date: 03/05/1996
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: de Fresart, Edouard D., Tam, Pak, Tsoi, Hak-Yam
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/962,725
• Time in Patent Office: 974 Days
• Field of Search: 257/339, 257/341, 257/342, 257/329, 257/330, 257/331, 257/333
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groove (122) or trench (152) design is incorporated to reduce JFET resistance (34). In a further embodiment, a gate dielectric layer having a thick portion (77,97,128,158) and thin portions (76,126,156) is incorporated to enhance switching characteristics and/or breakdown voltage.

Claims

1. A power MOSFET device comprising:

a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate forms a drain region;

a semiconductor layer formed on the semiconductor substrate, the semiconductor layer having a major surface;

a region of localized doping formed in the semiconductor layer, wherein the region of localized doping extends from the semiconductor substrate up to the major surface, the region of localized doping having the same conductivity type as the semiconductor layer and having a higher dopant concentration than the semiconductor layer;

first and second doped regions formed in the semiconductor layer and extending from the major surface, wherein the first and second doped regions are spaced apart from the region of localized doping, and wherein the first and second doped regions have a second conductivity type, and wherein at least a portion of the region of localized doping is between the first and second doped regions;

a first source region of the first conductivity type formed in the first doped region;

a second source region of the first conductivity type formed in the second doped region; and

a gate structure formed on the major surface.

2. The power MOSFET device of claim 1 wherein the gate structure includes a gate dielectric layer having a thick portion and thin portions.

3. The power MOSFET device of claim 2 wherein the thick portion comprises a LOCOS region.

4. The power MOSFET device of claim 1 further including a trench between the first and second source regions, and wherein the trench includes a bottom, and wherein a portion of the gate structure is formed in the trench.

5. The power MOSFET device of claim 4 wherein the gate structure includes a gate dielectric layer having a thick portion and thin portions, and wherein the thick portion is formed at the bottom of the trench.

6. The power MOSFET device of claim 1 further including a groove between the first and second source regions, and wherein the groove includes a lower surface, and wherein a portion of the gate structure is formed in the groove.

7. The power MOSFET device of claim 6 wherein the gate structure includes a gate dielectric layer having a thick portion and thin portions, and wherein the thick portion is formed on the lower surface of the groove.

8. An IGFET structure comprising:

a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate forms a drain region;

a semiconductor layer formed on the semiconductor substrate, wherein the semiconductor layer has a first major surface, and wherein the semiconductor layer forms an interface with the semiconductor substrate;

a region of localized doping formed in the semiconductor layer, the region of localized doping comprising the first conductivity type and having a higher dopant concentration than the semiconductor layer, wherein the region of localized doping extends from the first major surface to the semiconductor substrate, and wherein the region of localized doping has width;

first and second doped regions formed in the semiconductor layer and extending from the first major surface, wherein the first and second doped regions are spaced apart from the region of localized doping, and wherein the first and second doped regions have a second conductivity type;

a first source region of the first conductivity type formed in the first doped region;

a second source region of the first conductivity type formed in the second doped region; and

a gate structure formed on the first major surface and having a gate width, wherein the width of the region of localized doping is sufficiently less than the gate width near the interface between the semiconductor substrate and the semiconductor layer such that the on state resistance is decreased without significantly impacting breakdown voltage.

9. The IGFET structure of claim 8 wherein the gate structure includes a gate dielectric layer having a thick portion and thin portions.

10. The IGFET structure of claim 9 wherein the thick portion comprises a LOCOS region.

11. The IGFET structure of claim 8 further including a trench between the first and second source regions, and wherein the trench includes a bottom, and wherein a portion of the gate structure is formed in the trench.

12. The IGFET structure of claim 11 wherein the gate structure includes a gate dielectric layer having a thick portion and thin portions, and wherein the thick portion is formed at the bottom of the trench.

13. The IGFET structure of claim 8 further including a groove between the first and second source regions, and wherein the groove includes a lower surface, and wherein a portion of the gate structure is formed in the groove.

14. The IGFET structure of claim 13 wherein the gate structure includes a gate dielectric layer having a thick portion and thin portions, and wherein the thick portion is formed on the lower surface of the groove.