Semiconductor device and circuit board used therein

• US 6,084,295 A
• Filed: 09/04/1998
• Issued: 07/04/2000
• Est. Priority Date: 09/08/1997
• Status: Expired due to Term

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Akada, Hidemi, Horiuchi, Michio
• Primary Examiner(s): Trinh, Michael
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/148,330
• Time in Patent Office: 669 Days
• Field of Search: 257/738, 257/659, 257/700, 257/784, 257/690
• US Class Current: 257/690
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45565 Single coating layer
• CPC Class Codes: H01L 2224/4569 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4823 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor chip having electrode terminals arranged in an area-array manner is mounted on an upper surface of a first region of a circuit board. Bonding pads are provided on the upper surface of a second, different region of the circuit board, and are connected to electrode terminals on the upper surface of the chip with bonding wires covered with an electro-insulation coating. External connection terminals provided on an opposing surface of the second region of the circuit board in an area-array manner are electrically connected to the bonding pads by conductive vias provided through the circuit board in the thickness direction. An electro-insulation film covers the chip, including the bonding wire/electrode terminal connections, and the upper surface of the second region of the circuit board. An electro-conductive resin encapsulates the coated bonding wires and the electro-insulation film.

Claims

1. A semiconductor device, comprising:

a circuit board having a first surface, a second surface opposite to said first surface, a first region for receiving a semiconductor chip, and a second different region for receiving external connecting terminals;

a semiconductor chip having a first surface on which electrode terminals are arranged in an area-array manner and a second surface opposite to said first surface, said semiconductor chip being mounted on said circuit board in such a manner that said second surface of the semiconductor chip is in abutting contact with said first surface at the first region of the circuit board;

a plurality of bonding pads arranged on said first surface of the circuit board at said second region;

a plurality of bonding wires, each including a conductive wire and an electro-insulating coating for covering said conductive wire, for electrically connecting said electrode terminals of the chip to said bonding pads; and

external connecting terminals arranged on said second surface of the circuit board in an area-array manner at the second region, said external connecting terminals being electrically connected to said bonding pads by conductive vias provided through a thickness direction of said circuit board,

wherein connecting portions between said bonding wires and said electrode terminals, and connecting portions between said bonding wires and said bonding pads, are coated with an electro-insulation film,

wherein said semiconductor chip, said first surface of the second region of the circuit board, and said bonding wires, are encapsulated by an electro-conductive resin, and

wherein an electric potential of said electro-conductive resin is set at ground level.

2. A semiconductor device as set forth in claim 1, wherein said circuit board is provided with thermal vias in said first region which directly contact the chip.

3. A semiconductor device, comprising:

a circuit board having a first surface, a second surface opposite to said first surface, a first region for receiving a semiconductor chip, and a second, different region for receiving external connecting terminals;

a semiconductor chip having a first surface on which electrode terminals are arranged in an area-array manner and a second surface opposite to said first surface, said semiconductor chip being mounted on said circuit board in such a manner that said second surface of the semiconductor chip is in abutting contact with said first surface at the first region of the circuit board;

a plurality of conductive vias arranged in an area-array manner in said second region, and extending through a thickness direction of said circuit board, said vias being exposed approximately at said first surface of the circuit board to define a plurality of bonding pads;

a plurality of bonding wires, each including a conductive wire and an electro-insulation coating for covering said conductive wire, for electrically connecting said electrode terminals of the chip to said bonding pads; and

external connecting terminals at said conductive vias at said second surface of the circuit board,

wherein connecting portions between said bonding wires and said electrode terminals, and connecting portions between said bonding wires and said bonding pads, are coated with an electro-insulation film,

wherein said semiconductor chip, said first surface of the second region of the circuit board and said bonding wires are encapsulated by an electro-conductive resin, and

wherein an electric potential of said electro-conductive resin is set at ground level.

4. A semiconductor device as set forth in claim 3, wherein said circuit board is provided with thermal vias in said first region which directly contact the chip.

5. A semiconductor device as set forth in claim 3, wherein said conductive vias extend over said second surface of the circuit board to define said external terminals.

6. A semiconductor device as set forth in claim 3, wherein said circuit board has ground layers each surrounding an electro-insulation layer, which surrounds each conductive via.

7. A semiconductor device as set forth in claim 6, wherein each of said ground layers is annular-shaped.

8. A semiconductor device as set forth in claim 6, wherein said ground layers are arranged in a grid-like manner.

9. A circuit boards comprising:

a substrate having a first surface and a second surface opposite to said first surface;

a plurality of conductive vias arranged in an area-array manner and extending through a thickness direction of said substrate, said conductive vias being exposed approximately at said first surface to define a plurality of bonding pads;

a semiconductor chip located on the substrate and having electrode terminals;

a plurality of insulated bonding wires connecting the electrode terminals of the chip to the bonding pads;

external connecting terminals at said conductive vias at said second surface,

wherein the chip, connections between said bonding wires and said bonding pads and electrode terminals, and the circuit board, are coated with an electro-insulation film, and

wherein said semiconductor chip, electro-insulation film, and said insulated bonding wires, are encapsulated by an electro-conductive resin.

10. A circuit board as set forth in claim 9, wherein said conductive vias extend over said second surface of the substrate to define said external terminals.

11. A circuit board as set forth in claim 9, wherein said circuit board has ground layers, each surrounding an electro-insulation layer, which surrounds said conductive via.

12. A circuit board as set forth in claim 11, wherein each of said ground layers is annular-shaped.

13. A circuit board as set forth in claim 11, wherein said ground layers are arranged in a grid-like manner.