ATM multiplexing apparatus, ATM demultiplexing apparatus, and communication network with the apparatus

• US 6,084,889 A
• Filed: 02/12/1997
• Issued: 07/04/2000
• Est. Priority Date: 02/14/1996
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Murakami, Masaru
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Nguyen, Kim T.
• Application Number:
  US08/799,762
• Time in Patent Office: 1,238 Days
• Field of Search: 370/356, 370/373, 370/395, 370/474, 370/412, 370/416, 370/397, 370/352, 370/466, 370/399, 370/542, 370/535, 370/538, 370/539, 370/540, 370/541, 370/545
• US Class Current: 370/474
• CPC Class Codes: H04J 3/247 ATM or packet multiplexing
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5663 Support of N-ISDN
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An ATM multiplexing apparatus receives a multiplexed signal obtained by multiplexing a plurality of signals, converts each of a plurality of signals to a predetermined ATM cell according to a kind of the signal, then multiplexes these ATM cells, and outputs the multiplexed ATM cells. The ATM multiplexing apparatus includes a discriminator for discriminating each of a plurality of signals on the multiplexed signal, and a cell multiplexing apparatus for converting each of a plurality of signals on the multiplexed signal directly to a predetermined ATM cell on the basis of the output of the discriminator and outputs a stream of multiplexed ATM cells. On the other hand, an ATM demultiplexing apparatus receives a multiplexed stream of ATM cells, converts each ATM cell to a signal, then conducts multiplexing processing on the signals so as to correspond to a signal kind, converts the signals to a multiplexed signal, and outputs the multiplexed signal. The ATM demultiplexing apparatus includes an ATM cell disassembler for taking out each of a plurality of signals and a time stamp, and a signal multiplexer for converting a plurality of signals supplied from the ATM cell disassembler directly to a multiplexed signal on the basis of the time stamp and outputs the multiplexed signal.

Claims

1. An ATM demultiplexing apparatus for receiving a multiplexed ATM cell stream, converting said multiplexed ATM cell stream to a multiplexed signal having a second rate, and outputting said multiplexed signal, said ATM demultiplexing apparatus comprising:

an ATM cell disassembler which converts each ATM cell to a signal having a first rate and takes out each of said plurality of signals and a time stamp;

a memory which stores the signal and the time stamp supplied from said cell disassembler; and

a multiplexing controller which conducts multiplexing processing on said plurality of signals so as to correspond to a signal kind and generates multiplexing control signals from said time stamp stored in said memory, adjusts a signal readout rate, and inserts a part of said multiplexing control signals and said plurality of signals in predetermined positions in a frame of said multiplexed signal,

wherein a multiplexed signal obtained by multiplexing a plurality of signals read out from said memory is outputted, and

wherein said multiplexing controller comprises;

a table which stores beforehand a plurality of patterns of said multiplexing control signals to be inserted in said multiplexed signal,

a time stamp controller which generates a reference signal from the received time stamp and a clock of an ATM network, and

a pattern controller which selects one out of the patterns stored in the table on the basis of the reference signal and thereby adjusting a readout rate of a memory,

wherein the selected pattern and a plurality of signals are inserted in a frame of the multiplexed signal, and thereby synchronizing of each of a plurality of signals between a source node and destination node is assured.

2. A time stamp control circuit according to claim 1, comprising:

a time stamp generator which generates a time stamp from the clock of said ATM network and a number of bits of data read out from said memory; and

a comparator which compares a received time stamp with output of said time stamp generator,

wherein output of said comparator is outputted as the reference signal to be used by the pattern controller to adjust the data readout rate.