ADSL transceiver implemented with associated bit and energy loading integrated circuit
First Claim
1. An article of manufacture comprising:
- a processor accessible storage structure embodied in an integrated circuit; and
a processor executable routine stored in the storage structure, wherein the executable routine includes instructions for causing a processor to operate to configure data and energy loadings of K sub-channels of a high speed data transmission system so that it achieves a data rate R, the instructions including directions to the processor to execute the following operations;
(a) determining K signal-to-noise ratios associated with K sub-channels; and
(b) determining data capacities of each of the K sub-channels based on an evaluation of the following parameters;
i) the K signal-to-noise ratios; and
ii) said data rate R; and
iii) a number Nch of the K sub-channels having a non-zero bit capacity; and
wherein the data capacities can be determined by the processor executing one or more iterations of the operations of step (b) and Nch is calculated during each iteration.
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Accused Products
Abstract
An ADSL transceiver includes a new circuit and various iterative initialization and fine tuning routines for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal. The routines quickly converge to a target data rate by first estimating a power margin, and generating a bounded interval that includes the target rate. Thereafter, a binary iterative portion of the routine takes over and effectuates a final convergence to the target rate. A new mechanism for determining useful sub-channels is also disclosed. The resulting routines are extremely useful in that they maximize a data rate for a given power margin, and conversely, maximize a power margin for a given data rate. Two variants of a fine tuning process are also disclosed, and both can be used in combination to maximize system performance. The circuits and routines are preferably implemented in the form of an integrated circuit or module that includes a digital signal processor (DSP) and associated memory running a permanent binary coded executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. In an alternative form, the DSP may include a RAM that is loaded with the initialization and fine tuning routines from a computer readable media such as a floppy disk, a hard disk, a magnetic tape, a CD-ROM or other non-volatile computer readable storage media. In another embodiment, the circuits and routines may be implemented in the form of a software modem operating directly on a user'"'"'s machine instead of using a separate DSP and associated memory.
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Citations
34 Claims
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1. An article of manufacture comprising:
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a processor accessible storage structure embodied in an integrated circuit; and a processor executable routine stored in the storage structure, wherein the executable routine includes instructions for causing a processor to operate to configure data and energy loadings of K sub-channels of a high speed data transmission system so that it achieves a data rate R, the instructions including directions to the processor to execute the following operations; (a) determining K signal-to-noise ratios associated with K sub-channels; and (b) determining data capacities of each of the K sub-channels based on an evaluation of the following parameters; i) the K signal-to-noise ratios; and ii) said data rate R; and iii) a number Nch of the K sub-channels having a non-zero bit capacity; and wherein the data capacities can be determined by the processor executing one or more iterations of the operations of step (b) and Nch is calculated during each iteration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An article of manufacture comprising:
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a processor accessible readable media; and a processor executable routine stored in the media, wherein the executable routine causes a processor to operate to configure data and energy loadings of K sub-channels of a high speed data transmission system so that it achieves a data rate R by performing the following operations; (a) determining K signal-to-noise ratios associated with K sub-channels; and (b) determining data capacities of each of the K sub-channels based on an evaluation of the following parameters; i) the K signal-to-noise ratios; and ii) said data rate R; and iii) a number Nch of the K sub-channels having a non-zero bit capacity; and wherein the data capacities can be determined by the processor by executing one or more iterations of the operations of step (b) and Nch is calculated during each iteration. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method of manufacturing an integrated circuit, which circuit is used to configure data capacities of K sub-channels in a high speed transmission system using a data rate R, said method comprising the steps of:
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forming a memory storage structure such that it is accessible by a data processing unit; programming the memory storage structure such that it implements a processor executable routine, the routine including instructions for causing the processor to execute the following operations; (a) determining K signal-to-noise ratios associated with K sub-channels; and (b) determining data capacities of each of the K sub-channels based on an evaluation of the following parameters; i) the K signal-to-noise ratios; and ii) said data rate R; and iii) a number Nch of the K sub-channels having a non-zero bit capacity; and wherein the data capacities can be determined by the processor by one or more iterations of step (b) and Nch is calculated during each iteration. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification