Circuit for configuring and dynamically adapting data and energy parameters in a multi-channel communications system
First Claim
1. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a data rate R using N sub-channels, said circuit comprising:
- a sub-channel parameter memory for storing K signal-to-noise values associated with K sub-channels, where K<
N; and
a processing unit for determining and dynamically adapting data capacities of each of the K sub-channels based on an evaluation of the following parameters;
i) the K signal-to-noise ratios; and
ii) said data rate R; and
iii) a number Nch of the K sub-channels having a non-zero bit capacity; and
wherein the processing unit determines the data capacities in one or more iterations of a routine executed by the processing unit, and Nch is calculated during each iteration.
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Accused Products
Abstract
A circuit for optimizing and adapting the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing initial and adaptive sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (NCH) from iteration to iteration, which results in a more accurate loading of the sub-channels. If adjustments to bit loadings are required to achieve a particular initial target rate, the circuit first adjusts those sub-channels which will have the least effect on the overall system performance margin, so that compliance with system requirements is better achieved. In addition, an "iteration criteria" count can be incorporated to ensure that the initialization or adaptation of sub-channel loadings can be effectuated (at least to a very close order) in a predetermined and controlled fashion. The resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.
158 Citations
47 Claims
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1. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a data rate R using N sub-channels, said circuit comprising:
-
a sub-channel parameter memory for storing K signal-to-noise values associated with K sub-channels, where K<
N; anda processing unit for determining and dynamically adapting data capacities of each of the K sub-channels based on an evaluation of the following parameters; i) the K signal-to-noise ratios; and ii) said data rate R; and iii) a number Nch of the K sub-channels having a non-zero bit capacity; and wherein the processing unit determines the data capacities in one or more iterations of a routine executed by the processing unit, and Nch is calculated during each iteration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a target data rate R using K sub-channels, said circuit comprising:
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a sub-channel parameter memory for storing K signal-to-noise values associated with K sub-channels, where K<
N; anda processing unit for computing rough initial data capacities for each of the K sub-channels during an initialization procedure based on an evaluation of the following parameters; i) the K signal-to-noise ratios; and ii) said target data rate R; and iii) an iteration count M; and wherein the processing unit can determine the rough initial data capacities in M or fewer iterations of the initialization routine, and thereafter a fine tuning routine can be executed to determine more optimal capacities for the K sub-channels. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a rate R using K sub-channels, said circuit comprising:
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a sub-channel parameter memory for storing signal-to-noise values associated with some or all of said sub-channels; and a processing unit which can perform a configuration procedure and an adaptation routine to configure and adapt said system to operate at said rate R; and wherein the configuration and adaptation procedures include operations executed by the processing unit in one or more iterations, and during each iteration a sub-channel usability determination is made of which of the K sub-channels should be disabled, such determination being based on a consideration of a calculated minimum (bmin) and maximum (bmax) bit capacity of said sub-channels; and further wherein the processing unit allocates bit loadings only to the sub-channels which are not disabled during each iteration. - View Dependent Claims (28, 29, 30, 31, 32)
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33. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data at a data rate R using K sub-channels and with an overall target output power value P, said circuit comprising:
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a sub-channel parameter memory for storing signal to noise values associated with some or all of said sub-channels; and a processing unit which can perform a configuration procedure and an adaptation procedure to configure and adapt said system to operate at said data rate R; and wherein the configuration and adaptation procedures include operations executed by the processing unit in one or more iterations, and during each iteration; i) a determination is made of a proposed minimum (bmin) and a proposed maximum (bmax) bit loading for the data capacities of sub-channels that are not disabled; and ii) a determination is made of an output power value P'"'"' associated with such proposed loading; and iii) if P'"'"'>
P, bit capacity is removed in sorted order from those sub-channels which have the greatest power differential associated with carrying either bmin or bmax until P'"'"' is substantially equal to P. - View Dependent Claims (34, 35, 36, 37)
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38. A circuit for use in a high speed multi-channel transmission system, which system is intended to transmit data using K sub-channels, a total transmission power P, and a power margin γ
-
m, said circuit comprising;
a sub-channel parameter memory for storing data capacities associated with some or all of said sub-channels; and a processing unit which can perform a configuration procedure and an adaptation procedure to configure optimal data capacities; and wherein the procedures include operations executed by the processing unit to compute a transmission rate Btotal based on the following; i) a determination of a proposed minimum (bmin) and a proposed maximum (bmax) bit loading for the data capacities of sub-channels that are not disabled; and ii) a determination of an output power value P'"'"' and power modification factors, emax and emin associated with such bit loadings; and iii) replacing bmax with bmin, and emax with emin, for one or more sub-channels, until P'"'"'≦
P;whereby Btotal =Σ
bmax for all the sub-channels, and is maximized for such values of P and γ
m. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
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40. The circuit of claim 38, wherein Btotal can be adjusted to achieve a different rate Btarget by estimating an adjustment Δ
- γ
m to said system performance margin γ
m.
- γ
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41. The circuit of claim 38, wherein a target rate Btarget can be achieved by the processing unit by computing two values of Btotal, namely, Bmin and Bmax, which bound Btarget (Bmin <
- Btarget <
Bmax) and by the processing unit also computing a new Btotal based on a system performance margin γ
m '"'"' which is a function of γ
min and γ
max, where γ
min and γ
max are performance margins associated with Bmin and Bmax respectively.
- Btarget <
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42. The circuit of claim 41 wherein γ
-
m '"'"'=√
γ
min *√
γ
max and γ
'"'"'m is iteratively computed until Btotal converges to Btarget.
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m '"'"'=√
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43. The circuit of claim 38, wherein during the procedures, a number Nch of non-disabled sub-channels is calculated.
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44. The circuit of claim 38, wherein said processing unit is a signal processor, and further wherein the procedures are microcode routines which are executed by said signal processor to determine the optimal data capacities.
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45. The circuit of claim 38, wherein a bit error rate γ
- b for each sub-channel can be varied.
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46. The circuit of claim 38, wherein the processing unit dynamically adapts the data capacities in response to changes in characteristics of a transmission channel used by said transmission system.
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47. The circuit of claim 38 wherein the processing unit dynamically adapts the data capacities in response to changes in target data rate R for said transmission system.
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m, said circuit comprising;
Specification