Waiting circuit

• US 6,084,922 A
• Filed: 04/16/1998
• Issued: 07/04/2000
• Est. Priority Date: 04/17/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: YOZAN, Inc.
• Inventors: Zhou, Xuping, Shou, Guoliang, Zhou, Changming
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US09/061,097
• Time in Patent Office: 810 Days
• Field of Search: 375/316, 375/343, 375/340, 375/365, 375/366, 455/343
• US Class Current: 375/316
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A waiting circuit which is utilized in a mobile communication system. The waiting circuit detects a predetermined signal from a base station. The waiting circuit starts other circuits in the mobile communication system which are in a sleep mode when the predetermined signal is received. The predetermined signal is generated in the base station. The predetermined signal has a speed equal to a predetermined symbol rate and is modulated to be an intermediate frequency signal. The intermediate frequency signal is sampled in response to a sampling clock that has a speed equal to an integer times the symbol rate. The sampled intermediate frequency signal is input to a match filter which multiplies the sample signal by a predetermined sequence of coefficients.

Claims

1. A waiting circuit incorporated within a portable terminal of a mobile communication system, for detecting a predetermined signal from a base station to start other circuits which are in a sleep mode, said predetermined signal being generated in said base station having a speed corresponding to a predetermined symbol rate, said predetermined signal being modulated in said base station to be an intermediate frequency signal having a frequency higher than a frequency of said symbol rate, comprising:

a sub-sampling circuit for sampling said intermediate frequency signal in response to a sampling clock having a speed equal to an integer times said symbol rate;

a matched filter for multiplying said sampled intermediate frequency signal by a predetermined sequence of coefficients corresponding to said intermediate frequency signal, and producing a produces a matched filter signal; and

a control circuit for starting said other circuits when said matched filter signal indicates that said predetermined signal is received.

2. The waiting circuit as claimed in claim 1, wherein said predetermined signal comprises a UW signal for establishing a word synchronization of a burst signal, a CI signal for identifying said portable terminal, a DATA1 signal identifying a service type;

and

sequences of coefficients for detecting UW, CI or DATA1 are selectively input to said matched filter.

3. The waiting circuit as claimed in claim 2, further comprising a judgment circuit which successively performs detection of said UW, CI and DATA1 signals until none of said UW, CI or DATA1 signal is detected.

4. The waiting circuit as claimed in claim 2, wherein said predetermined signal further comprises a DATA2 signal which includes additional information, and is detectable after DATA1 is detected.

8. The waiting circuit as claimed in claim 2, wherein:

said predetermined signal comprises a UW signal for establishing a word synchronization of a burst signal, a CI signal for identifying said portable terminal, a DATA1 signal identifying a service type; and

sequences of coefficients for detecting UW, CI or DATA1 are selectively input to said matched filter.

9. The waiting circuit as claimed in claim 8, further comprising a judgment circuit which successively performs detection of said UW, CI and DATA1 signals until none of said UW, CI or DATA1 signal is detected.

10. The waiting circuit as claimed in claim 9, wherein said predetermined signal further comprises a DATA2 signal which includes additional information and is detectable after DATA1 is detected.

12. The waiting circuit as claimed in claim 3, wherein there are two intermediate frequency signals.

13. The waiting circuit as claimed in claim 9, wherein said frequency conversion circuit hard-limits said received signal to generate a signal similar to a binary signal.

5. A waiting circuit incorporated within a portable terminal of a mobile communication system, for detecting a predetermined signal from a base station to start other circuit which are in a sleep mode, said predetermined signal being generated in said base station having a speed corresponding to a predetermined symbol rate, said predetermined signal being step-wisely modulated in said base station to be a plurality of intermediate frequency signals being step-wisely higher one after another, an intermediate frequency signal of a final step being modulated by a carrier signal, said waiting circuit comprising:

a frequency conversion circuit for converting a received signal having a carrier wave frequency into an intermediate frequency signal having the lowest frequency of said plurality intermediate frequency signals;

a sub-sampling circuit for sampling said intermediate frequency signal having said lowest frequency in response to a sampling clock having a speed equal to an integer times said symbol rate;

a matched filter for multiplying said sampled intermediate frequency signal by a predetermined sequence of coefficients corresponding to said intermediate frequency signal having the lowest frequency, and producing a matched filter signal; and

a control circuit for starting said other circuits when said matched filter signal indicates that said predetermined signal is received.

6. The waiting circuit as claimed in claim 5, wherein there are two intermediate frequency signals.

7. The waiting circuit as claimed in claim 6, wherein said frequency conversion circuit hard-limits said received signal to generate a signal similar to a binary signal.

11. A waiting circuit incorporated within a portable terminal of a mobile communication system, for detecting a predetermined signal from a base station to start other circuits which are in a sleep mode, said predetermined signal being generated in said base station having a speed corresponding to a predetermined signal rate, and is quadratically modulated in said base station into in-phase and quadrature phase components, each of said components being step-wisely modulated in said base station to be a plurality of intermediate frequency signals being step-wisely higher one after another, an intermediate frequency signal of a final step being modulated by a carrier signal, said waiting circuit comprising:

a frequency conversion circuit for converting a received signal having a carrier wave frequency into an intermediate frequency signal having the lowest frequency of said plurality of intermediate frequency signals;

a sub-sampling circuit for sampling said intermediate frequency signal having said lowest frequency in response to two phase sampling clocks each having a speed equal to an integer times said symbol rate, wherein each of said two phase sampling clocks are shifted from each other by a quarter of a cycle of said lowest intermediate frequency;

a complex matched filter for multiplying said sampled intermediate frequency signals of both of said sampling clocks by a predetermined sequence of coefficients corresponding to said intermediate frequency signal having said lowest frequency, and producing a complex matched filter signal; and

a control circuit for starting said other circuits when said complex matched filter signal indicates that said predetermined signal is received.

14. The waiting circuit as claimed in claim 11, wherein:

said predetermined signal comprises a UW signal for establishing a word synchronization of a burst signal, a CI signal for identifying said portable terminal, a DATA1 signal identifying a service type; and

sequences of coefficients for detecting UW, CI or DATA1 are selectively input to said complex matched filter.

15. The waiting circuit as claimed in claim 14, further comprising a judgment circuit which successively performs detection of said UW, CI and DATA1 signals until none of said UW, CI or DATA1 signal is detected.

16. The waiting circuit as claimed in claim 15, wherein said predetermined signal further comprises a DATA2 signal which includes additional information and is detectable after DATA1 is detected.