Data processing system and method thereof

• US 6,085,275 A
• Filed: 02/09/1995
• Issued: 07/04/2000
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Seaton, Robert W. Jr., Osborn, Stephen G., Tomazin, Thomas J., Lawell, Terry G., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US08/389,511
• Time in Patent Office: 1,972 Days
• Field of Search: 395/325, 395/800, 395/280, 395/200.15, 710/131, 712/10, 712/11, 712/18, 370/355
• US Class Current: 710/316
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A data processor, comprising:

a first port;

a second port;

a first storage circuit for storing a plurality of control values;

a second storage circuit;

a first switch circuit coupled between the first port and the second port, the first switch circuit being in either a conducting mode or a non-conducting mode in response to a first one of the plurality of control values; and

a first tap circuit coupled between the first port and the second storage circuit, the first tap circuit being in either the conducting mode or the non-conducting mode in response to a second one of the plurality of control values,

wherein if first information is transferred into said data processor by way of said first port said first tap circuit does not require that said first information include any address information in order for said first tap circuit to determine if at least a portion of said first information is to be stored in said data processor.

2. The data processor of claim 1 wherein the first switch circuit couples the first port to the second port when the first switch circuit is in the conducting mode.

3. The data processor of claim 1 wherein the first port is not coupled to the second port when the first switch circuit is in the non-conducting mode.

4. The data processor of claim 1 further comprising:

interface means, coupled to the first storage circuit, the interface means transferring the plurality of control values to the first storage circuit in response to a software program.

5. The data processor of claim 4 further comprising:

an instruction storage circuit internal to the data processor for storing the software program, the instruction storage circuit being coupled to the interface means.

6. The data processor of claim 4 further comprising:

a memory circuit external to the data processor for of storing the software program, the memory circuit being coupled to the interface means.

7. The data processor of claim 4, wherein said first and second ones of the plurality of control values are dynamically alterable by said software program.

8. The data processor of claim 1 wherein the first tap circuit couples the first port to the second storage circuit when the first tap circuit is in the conducting mode.

9. The data processor of claim 1 wherein the first tap circuit does not couple the first port to the second storage circuit when the first tap circuit is in the non-conducting mode.

10. The data processor of claim 1 further comprising:

a second tap circuit coupled between the second port and the second storage circuit, the second tap circuit being in either the conducting mode or the non-conducting mode in response to a third one of the plurality of control bits,

wherein if second information is transferred into said data processor by way of said second port, said second tap circuit does not require that said second information include any address information in order for said second tap circuit to determine if at least a portion of said second information is to be stored in said data processor.

11. The data processor of claim 10 wherein the second tap circuit couples the second port to the second storage circuit when the second tap circuit is in the conducting mode.

12. The data processor of claim 10 wherein the second tap circuit does not couple the second port to the second storage circuit when the second tap circuit is in the non-conducting mode.

13. The data processor of claim 10 further comprising:

a third port;

a fourth port;

a second switch circuit coupled between the third port and the fourth port, the second switch circuit being in either the conducting or the non-conducting mode in response to a fourth one of the plurality of control values;

a third tap circuit coupled between the third port and the second storage circuit, the third tap circuit being in either the conducting mode or the non-conducting mode in response to a fifth one of the plurality of control values; and

a fourth tap circuit coupled between the fourth port and the second storage circuit, the fourth tap circuit being in either the conducting mode or the non-conducting mode in response to a sixth one of the plurality of control values,

wherein if third information is transferred into said data processor by way of said third port, said third tap circuit does not require that said third information include any address information in order for said third tap circuit to determine if at least a portion of said third information is to be stored in said data processor.

14. The data processor of claim 1 wherein the first storage circuit comprises at least one programmable control register.

15. A data processor, comprising:

a first port for communicating a digital message wherein the digital message does not have any destination address;

a second port for communicating the digital message;

a first storage circuit for storing a control value;

a second storage circuit;

a first switch circuit coupled between the first port and the second port, the first switch circuit being in one of a conducting mode and a non-conducting mode in response to a first portion of the control value; and

a first tap circuit coupled between the first port and the second storage circuit, the first tap circuit being in one of the conducting mode and the non-conducting mode in response to a second portion of the control values

wherein operation of said first tap circuit is independent of any destination address of the digital message.

16. The data processor of claim 15 wherein the digital message is transferred between the first port and the second port when the first switch circuit is in the conducting mode.

17. The data processor of claim 15 wherein no digital message is transferred between the first port and the second port when the first switch circuit is in the non-conducting mode.

18. The data processor of claim 15 wherein the digital message is transferred from the first port to the second storage circuit when the first tap circuit is in the conducting mode, the second storage circuit storing the digital data.

19. The data processor of claim 15 wherein no digital message is transferred from the first port to the second storage circuit when the first tap circuit is in the non-conducting mode.

20. The data processor of claim 15 wherein the control value is provided to the first storage circuit in response to a software program.

21. The data processor of claim 20 further comprising:

an instruction storage circuit internal to the data processor for storing the software program.

22. The data processor of claim 21 further comprising:

a memory external to the data processor for storing an initialization program.

23. The data processor of claim 15 further comprising:

a reset circuit for setting the control value to a predetermined value when the data processor is reset.

24. The data processor of claim 15 further comprising:

a second tap circuit coupled between the second port and the second storage circuit, the second tap circuit being in one of the conducting mode and the non-conducting mode in response to a third portion of the control value,

wherein operation of said second tap circuit is independent of any destination address of the digital message.

25. The data processor of claim 24 further comprising:

a third port for communicating digital data;

a fourth port for communicating digital data;

a second switch circuit coupled between the third port and the fourth port, the second switch circuit being in one of the conducting and the non-conducting mode in response to a fourth portion of the control value;

a third tap circuit coupled between the third port and the second storage circuit, the third tap circuit being in one of the conducting and the non-conducting mode in response to a fifth portion of the control value; and

a fourth tap circuit coupled between the fourth port and the second storage circuit, the fourth tap circuit being in one of the conducting and the non-conducting mode in response to a sixth portion of the control value,

wherein operation of said third tap circuit is independent of any destination address of the digital message and wherein operation of said fourth tap circuit is independent of any destination address of the digital message.

26. The data processor of claim 15 further comprising:

mode selection means for enabling the data processor to communicate in one of a first mode of operation and a second mode of operation, wherein;

when the data processor is in the first mode of operation, an external processor uses the first port and the second port together to access the first storage circuit without using the control value to control behavior of said first switch circuit and said first tap circuit; and

when the data processor is in the second mode of operation, the data processor is selectively enabled to communicate digital information in response to the control value stored in the first storage circuit, the plurality of control values selectively enabling both the first port and the second port to independently communicate digital data.

27. The data processor of claim 15 further comprising:

a holding register, the holding register storing digital data transferred between the first port and the second port when the first switch circuit is in the conducting mode.

28. A method for communicating digital data in a data processor, the data processor having a first port for communicating digital data, a second port for communicating digital data, a first storage circuit for storing a control value, and a second storage circuit for storing digital data, the method comprising the steps of:

providing the digital data to the data processor without providing any corresponding destination address for the digital data;

coupling a first switch circuit between the first port and the second port;

selecting one of a conducting mode and a non-conducting mode of the first switch circuit in response to a first portion of the control value and independent of any corresponding destination address for the digital data;

coupling a first tap circuit between the first port and the second storage circuit; and

selecting one of the conducting mode and the non-conducting mode of the first tap circuit in response to a second portion of the control value and independent of any corresponding destination address for the digital data.

29. The method of claim 28 wherein the step of selecting one of the conducting mode and the non-conducting mode of the first switch circuit further comprises the steps of:

transferring digital data between the first port and the second port when the first portion of the control value has a first value; and

preventing transfer of digital data between the first port and the second port when the first portion of the control value has a second value.

30. The method of claim 28 wherein the step of selecting one of the conducting mode and the non-conducting mode of the first tap circuit further comprises the steps of:

transferring digital data from the first port to the second storage circuit when the second portion of the control value has a first value; and

preventing transfer of digital data between the first port and the second storage circuit when the second portion of the control value has a second value.

31. The method of claim 28 further comprising the step of:

enabling a software program to provide the control value to the first storage circuit.

32. The method of claim 31 further comprising the step of:

enabling the software program to dynamically modify the control value while the data processor executes an instruction.

33. The method of claim 31 further comprising the step of:

selectively storing the software program in an instruction storage circuit internal to the data processor.

34. The method of claim 33 further comprising the step of:

selectively storing the software program in a memory external to the data processor.

35. The method of claim 28 further comprising the step of:

enabling a reset circuit to provide the control value to the first storage circuit.

36. The method of claim 28 further comprising the steps of:

coupling a second tap circuit between the second port and the second storage circuit; and

selecting one of the conducting mode and the non-conducting mode of the second tap circuit in response to a third portion of the control value and independent of any corresponding destination address for the digital data.

37. The method of claim 36 wherein the step of determining a mode of the second tap circuit further comprises the steps of:

transferring digital data from the second port to the second storage circuit when the third portion of the control value has a first

preventing transfer of digital data between the second port and the second storage circuit when the third portion of the control value has a second value.

38. The method of claim 37 further comprising the steps of:

coupling a second switch circuit between a third port and a fourth port;

selecting one of the conducting mode and the non-conducting mode of the second switch circuit in response to a fourth portion of the control value;

coupling a third tap circuit between the third port and the second storage circuit;

selecting one of the conducting mode and the non-conducting mode of the third tap circuit in response to a fifth portion of the control value and independent of any corresponding destination address for the digital data;

coupling a fourth tap circuit between the fourth port and the second storage circuit; and

selecting one of the conducting mode and the non-conducting mode of the fourth tap circuit in response to a sixth portion of the control value and independent of any corresponding destination address for the digital data.

39. A data processing system, comprising:

a plurality of data processors wherein each one of the plurality of data processors, comprising;

a plurality of ports for communicating digital data;

a first storage circuit for storing a control value;

a second storage circuit;

a plurality of switch circuits, each of the plurality of switch circuits being coupled between two of the plurality of ports, each of the plurality of switch circuits being in one of a conducting mode and a non-conducting mode in response to a first portion of the control value;

a plurality of tap circuits, each of the plurality of tap circuits being coupled between a predetermined one of the plurality of ports and the second storage circuit, each of the plurality of tap circuits being in one of the conducting mode and the non-conducting mode in response to a second portion of the control value; and

a first conductor for coupling one of the plurality of ports of a first one of the plurality of data processors to one of the plurality of ports of a second one of the plurality of data processors to selectively communicate digital data between the first one of the plurality of data processors and the second one of the plurality of data processors, and

wherein each of said plurality of tap circuits makes a determination as to whether or not at least a portion of digital data incoming to the corresponding predetermined one of the plurality of ports is to be stored, and wherein each of said plurality of tap circuits makes said determination without using destination address information provided as part of the incoming digital data.

40. The data processing system of claim 39 wherein digital data is transferred from the first one of the plurality of data processors to the second one of the plurality of data processors when a predetermined one of the plurality of switch circuits is in the conducting mode.

41. The data processing system of claim 39 wherein digital data is transferred into the second storage circuit of one of the plurality of data processors when any one of the plurality of tap circuits is in the conducting mode and the digital data is received at the corresponding predetermined one of the plurality of ports.

42. The data processing system of claim 39 wherein the plurality of switch circuits comprises:

a first switch circuit coupled between a first one of the plurality of ports and a second one of the plurality of ports, the first switch circuit being in one of the conducting mode and the non-conducting mode in response to a first portion of the control value; and

a second switch circuit coupled between a third one of the plurality of ports and a fourth one of the plurality of ports, the second switch circuit being in one of the conducting and non-conducting modes in response to a second portion of the control value.

43. The data processing system of claim 42 wherein the plurality of tap circuits comprises:

a first tap circuit coupled between the first one of the plurality of ports and the second storage circuit, the first tap circuit being in one of the non-conducting mode and the conducting mode in response to a third portion of the control value;

a second tap circuit coupled between the second one of the plurality of ports and the second storage circuit, the second tap circuit being in one of the non-conducting mode and the conducting mode in response to a fourth portion of the control value;

a third tap circuit coupled between the third one of the plurality of ports and the second storage circuit, the third tap circuit being in one of the non-conducting mode and the conducting mode in response to a fifth portion of the control value; and

a fourth tap circuit coupled between the fourth one of the plurality of ports and the second storage circuit, the fourth tap circuit being in one of the non-conducting mode and the conducting mode in response to a sixth portion of the control value.

44. The data processing system of claim 39 wherein each of the plurality of data processors are arranged in a plurality of rows and a plurality of columns.

45. The data processing system of claim 39 wherein the plurality of data processors is arranged in at least one row.

46. The data processing system of claim 39 wherein the plurality of data processors is arranged in at least one column.

47. A data processor, comprising:

a first port;

a second port;

a first storage circuit for storing a plurality of control values;

a second storage circuit; and

a tap circuit coupled between the first port and the second storage circuit,

wherein if information is transferred into said data processor by way of said first port, said tap circuit uses one of the plurality of control values to determine if at least a portion of said information is to be stored in said data processor, and said tap circuit does not require that said information include any address information in order for said first tap circuit to determine if at least a portion of said information is to be stored in said data processor.