Interrupt and message batching apparatus and method
First Claim
1. A system for handling I/O messages transmitted over an I/O bus, comprising:
- a processor complex connected to the I/O bus, said processor complex including a memory device having a message queue structure;
an I/O adapter connected to the I/O bus, said I/O adapter includinga message processor to process messages, to generate messages, and to send messages to the message queue structure;
a signalling timer timing an interval beginning with placing a message in the message queue structure; and
decision logic deciding when to signal an interrupt to said processor complex;
said decision logic programs the signalling timer with a fast signal time value if the message has a relatively short latency period or with a slow signal time value if the message has a relatively long latency period, andthe decision logic starts the signalling timer when the message is enqueued, andsaid decision logic signalling an interrupt to said processor complex when the signalling timer has elapsed.
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Accused Products
Abstract
An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.
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Citations
39 Claims
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1. A system for handling I/O messages transmitted over an I/O bus, comprising:
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a processor complex connected to the I/O bus, said processor complex including a memory device having a message queue structure; an I/O adapter connected to the I/O bus, said I/O adapter including a message processor to process messages, to generate messages, and to send messages to the message queue structure; a signalling timer timing an interval beginning with placing a message in the message queue structure; and decision logic deciding when to signal an interrupt to said processor complex; said decision logic programs the signalling timer with a fast signal time value if the message has a relatively short latency period or with a slow signal time value if the message has a relatively long latency period, and the decision logic starts the signalling timer when the message is enqueued, and said decision logic signalling an interrupt to said processor complex when the signalling timer has elapsed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. In a computer system having a first and second device interconnected by a bus, an interrupt decision sequence, comprising:
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sending a message from the first device to the second device, enqueing a message in a message queue located in the second device, programming a signalling timer with a fast signal time value if the first device has a relatively short latency period or with a slow signal time value if the first device has a relatively long latency period, starting the signalling timer with the programmed response time value after completion of said enqueing step, and signalling an interrupt to the second device when the the signalling timer has elapsed. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of managing a first message queue in a computer system:
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providing the first message queue in a memory of the computer system, generating a first message, enqueing the first message in the first message queue of the memory, programming a signalling timer with a fast signal time value if the first message has a relatively short latency period or with a slow signal time value if the first message has a relatively long latency period in response to said enqueing step enqueing the first message, and signalling a processor complex interrupt when the signalling timer has elapsed. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification