Communications interface adapter for a computer system including posting of system interrupt status

• US 6,085,278 A
• Filed: 06/02/1998
• Issued: 07/04/2000
• Est. Priority Date: 06/02/1998
• Status: Expired due to Term

• Current Assignee: Wi-LAN Inc.
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Gates, Stillman F., Davoudi, Jamileh
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/089,068
• Time in Patent Office: 763 Days
• Field of Search: 710/36, 710/22, 710/48, 710/47, 710/100, 710/130, 710/129, 710/260, 710/263, 710/52, 710/62, 710/266, 712/244, 714/2, 714/25, 714/47, 711/156, 370/242, 709/301, 709/107
• US Class Current: 710/263
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer

Abstract

To facilitate access of interrupt status information, interrupt posting status. POST_-- STAT registers are readable by a host driver routine to quickly supply information relating to a functional block which has given rise to an interrupt status condition. The interrupt posting status POST_-- STAT registers contain a summary of interrupt status information. The host driver may then read the interrupt posting status POST_-- STAT register corresponding to the functional block to further investigate the cause of the interrupt status. System memory includes a mirror storage of the interrupt posting status POST_-- STAT registers that is transferred to the mirror storage by a direct memory access (DMA) operation. Values in the system mirror storage are updated automatically when a change occurs in a value within the interrupt posting status POST_-- STAT registers. A host system software driver accesses the interrupt posting status POST_-- STAT registers via a bus access operation, changes a bit in a POST_-- STAT register, and monitors the result of the access and bit change in the mirror of the POST_-- STAT register in the system memory without a further bus read access. Advantageously, multiple accesses through the bus to verify when the written value status is correct is eliminated.

Claims

1. A bus interface apparatus comprising:

a host interface that is connectable to a bus, the bus being connectable to a host system, the host system including a host driver; and

a command channel control and monitoring circuit coupled to the host interface and including a data buffer, the command channel control and monitoring circuit controlling and monitoring communication functionality between the data buffer and the bus;

the command channel control and monitoring circuit including an interrupt posting status register that is readable by the host driver, the interrupt posting status register consolidating a summary of interrupt status information of interrupts arising from a plurality of functional blocks coupled to the bus, the interrupt posting status register being readable by the host driver to investigate a cause of the interrupt statue;

.

2. A bus interface apparatus according to claim 1 wherein:

the command channel control and monitoring circuit is a DMA circuit supporting DMA access of the interrupt posting status register via the bus.

3. A bus interface apparatus according to claim 1 wherein the bus is a Peripheral Component Interface (PCI) bus.

4. A bus interface apparatus according to claim 1 further comprising:

the host system including a system memory with a mirror storage of the interrupt posting status register that receives data transmitted from the interrupt posting status register by a direct memory access (DMA) operation, values in the mirror storage of the interrupt posting status register being updated automatically when a change occurs in a value within the interrupt posting status register in the command channel control and monitoring circuit.

5. A bus interface apparatus according to claim 4 wherein:

the host system host driver includes a routine for accessing the interrupt posting status register via a bus access operation, changing a bit in a register of the interrupt posting status register, and monitoring the result of the access and bit change in the mirror of the register in the system memory without and additional bus read access.

6. A bus interface apparatus according to claim 4 wherein:

an interrupt value is preposted in the mirror storage of the interrupt posting status register before a bus interrupt signal is activated when an automatic interrupt posting status update functionality is enabled; and

the bus interrupt signal is activated without delay when the automatic interrupt posting status update functionality is not enabled.

7. A bus interface apparatus according to claim 1 wherein:

the command channel control and monitoring circuit functionality includes transmission of data from the data buffer over the bus using a direct memory access (DMA) operation including a read and compare option so that interrupt status information is posted into a storage in the system memory that mirrors the interrupt posting status register and checks for any update during the direct memory access operation.

8. A bus interface apparatus according to claim 1 wherein:

the command channel control and monitoring circuit handles dual interrupt requests including one interrupt request for normal interrupts and a second interrupt request for abnormal interrupts.

9. A bus interface apparatus according to claim 8 wherein:

the interrupt request for normal interrupts and the interrupt request for abnormal interrupts are programmable and are selectively merged into one interrupt.

10. A bus interface apparatus according to claim 1 wherein:

a plurality of command completions are queued on a single interrupt.

11. A bus interface apparatus according to claim 1 further comprising:

an interrupt posting enable register having a plurality of status bits, the interrupt posting enable register being coupled to the command channel control and monitoring circuit and individually controlling issue of interrupts for each status bit.

12. A bus interface apparatus according to claim 1 further comprising:

a device configuration register having a plurality of bits, the device configuration register being coupled to the command channel control and monitoring circuit and individually enabling and disabling a read and compare operation of posted interrupt status that controls automatic and immediate reading and comparing a selected storage location following a write of the selected storage location.

13. A bus interface apparatus comprising:

a bus;

a host system coupled to the bus, the host system including a system memory;

a host interface that is connectable to the bus for communicative interfacing to the host system; and

a command channel control and monitoring circuit coupled to the host interface and including a data buffer, the command channel control and monitoring circuit controlling and monitoring communication functionality between the data buffer and the bus;

the command channel control and monitoring circuit including an interrupt posting status register consolidating a summary of interrupt status information of interrupts arising from a plurality of functional blocks coupled to the bus, the system memory including a mirror storage of the interrupt posting status register that receives data transmitted from the interrupt posting status register by a direct memory access (DMA) operation, values in the mirror storage of the interrupt posting status register being updated automatically when a change occurs in a value within the interrupt posting status register in the command channel control and monitoring circuit.

14. A bus interface apparatus according to claim 13 wherein the bus is a Peripheral Component Interface (PCI) bus.

15. A bus interface apparatus according to claim 13 wherein:

the host system includes a host driver, the host driver including a routine for accessing the interrupt posting status register via a bus access operation, changing a bit in a register of the interrupt posting status register, and monitoring the result of the access and bit change in the mirror of the register in the system memory without an additional bus read access.

16. A bus interface apparatus according to claim 13 wherein:

an interrupt value is preposted in the mirror storage of the interrupt posting status register before a bus interrupt signal is activated when an automatic interrupt posting status update functionality is enabled; and

the bus interrupt signal is activated without delay when the automatic interrupt posting status update functionality is not enabled.

17. A bus interface apparatus according to claim 13 wherein:

the command channel control and monitoring circuit functionality includes transmission of data from the data buffer over the bus using a direct memory access (DMA) operation including a read and compare option so that interrupt status information is posted into a storage in the system memory that mirrors the interrupt posting status register and checks for any update during the direct memory access operation.

18. A bus interface apparatus according to claim 13 wherein:

the command channel control and monitoring circuit handles dual interrupt requests including one interrupt request for normal interrupts and a second interrupt request for abnormal interrupts.

19. A bus interface apparatus according to claim 18 wherein:

the interrupt request for normal interrupts and the interrupt request for abnormal interrupts are programmable and are selectively merged into one interrupt.

20. A bus interface apparatus according to claim 13 wherein:

a plurality of command completions are queued on a single interrupt.

21. A bus interface apparatus according to claim 13 further comprising:

an interrupt posting enable register having a plurality of status bits, the interrupt posting enable register being coupled to the command channel control and monitoring circuit and individually controlling issue of interrupts for each status bit.

22. A bus interface apparatus according to claim 13 further comprising:

a device configuration register having a plurality of bits, the device configuration register being coupled to the command channel control and monitoring circuit and individually enabling and disabling a read and compare operation of posted interrupt status that controls automatic and immediate reading and comparing a selected storage location following a write of the selected storage location.

23. A bus interface apparatus comprising:

a host interface that is connectable to a bus, the bus being connectable to a host system, the host system including a host driver and a system memory; and

a command channel control and monitoring circuit coupled to the host interface and including a data buffer, the command channel control and monitoring circuit including an interrupt posting status register that is readable by the host driver, the command channel control and monitoring circuit capable of controlling and monitoring communication functionality between the data buffer and the bus, the communication functionality including transmission of data from the data buffer over the bus using a direct memory access (DMA) operation including a read and compare option so that interrupt status information is posted into a storage in the system memory that mirrors the interrupt posting status register and checks for any update during the direct memory access operation.

24. A bus interface apparatus according to claim 23 wherein the bus is a Peripheral Component Interface (PCI) bus.

25. A bus interface apparatus according to claim 23 further comprising:

the host system wherein;

the system memory includes a mirror storage of the interrupt posting status register that receives data transmitted from the interrupt posting status register by a direct memory access (DMA) operation, values in the mirror storage of the interrupt posting status register being updated automatically when a change occurs in a value within the interrupt posting status register in the command channel control and monitoring circuit.

26. A bus interface apparatus according to claim 25 wherein:

the host system host driver includes a routine for accessing the interrupt posting status register via a bus access operation, changing a bit in a register of the interrupt posting status register, and monitoring the result of the access and bit change in the mirror of the register in the system memory without an additional bus read access.

27. A bus interface apparatus according to claim 25 wherein:

an interrupt value is preposted in the mirror storage of the interrupt posting status register before a bus interrupt signal is activated when an automatic interrupt posting status update functionality is enabled; and

the bus interrupt signal is activated without delay when the automatic interrupt posting status update functionality is not enabled.

28. A bus interface apparatus according to claim 23 wherein:

the command channel control and monitoring circuit functionality includes transmission of data from the data buffer over the bus using a direct memory access (DMA) operation including a read and compare option so that interrupt status information is posted into a storage in the system memory that mirrors the interrupt posting status register and checks for any update during the direct memory access operation.

29. A bus interface apparatus according to claim 23 wherein:

the command channel control and monitoring circuit handles dual interrupt requests including one interrupt request for normal interrupts arid a second interrupt request for abnormal interrupts.

30. A bus interface apparatus according to claim 29 wherein:

the interrupt request for normal interrupts and the interrupt request for abnormal interrupts are programmable and are selectively merged into one interrupt.

31. A bus interface apparatus according to claim 23 wherein:

a plurality of command completions are queued on a single interrupt.

32. A bus interface apparatus according to claim 23 further comprising:

an interrupt posting enable register having a plurality of status bits, the interrupt posting enable register being coupled to the command channel control and monitoring circuit and individually controlling issue of interrupts for each status bit.

33. A bus interface apparatus according to claim 23 further comprising:

a device configuration register having a plurality of bits, the device configuration register being coupled to the command channel control and monitoring circuit and individually enabling and disabling a read and compare operation of posted interrupt status that controls automatic and immediate reading and comparing a selected storage location following a write of the selected storage location.

34. A bus interface apparatus comprising:

a bus;

a host system;

means connectable to the bus for interfacing [a] the host system to the bus, the host system including;

a host driver;

means for storing a mirror image of the summary of interrupt status information that is posted by the posting means; and

means for automatically updating the mirror image when a change occurs in the summary of interrupt status information;

a data buffer;

means coupled to the interfacing means and coupled to the data buffer for controlling and monitoring communication functionality between the data buffer and the bus, the controlling and monitoring means further including;

means for consolidating a summary of interrupt status information of interrupts arising from a plurality of functional blocks coupled to the bus; and

means for posting the summary of interrupt status information, the posting means being readable by the host driver.

35. A bus interface apparatus according to claim 34 wherein:

the host system further includes;

means for accessing the summary of interrupt status information via a bus access operation;

means for changing the summary of interrupt status information; and

means for monitoring the result of the change in the summary of interrupt status information and in the mirror image without an additional bus read access.

36. A bus interface apparatus according to claim 34 further comprising:

means for preposting an interrupt value in the mirror image before a bus interrupt signal is activated when an automatic interrupt posting status update functionality is enabled; and

means for activating the bus interrupt signal without delay when the automatic interrupt posting status update functionality is not enabled.

37. A bus interface apparatus according to claim 34 further comprising:

means for transmitting data from the data buffer over the bus using a direct memory access (DMA) operation including a read and compare option so that interrupt status information is posted into a storage in the system memory that mirrors the interrupt posting status register and checks for any update during the direct memory access operation.

38. A bus interface apparatus according to claim 34 further comprising:

means for handling dual interrupt requests including one interrupt request for normal interrupts and a second interrupt request for abnormal interrupts.

39. A bus interface apparatus according to claim 38 further comprising:

means for programming interrupt requests for normal interrupts and for abnormal interrupts; and

means for merging the normal interrupt requests and abnormal interrupt requests into a single interrupt.

40. A bus interface apparatus according to claim 38 further comprising:

means for queuing a plurality of command completions on a single interrupt.

41. A bus interface apparatus according to claim 34 further comprising:

means for individually controlling issue of a plurality of interrupts.

42. A method of operating a bus interface for interfacing a host system to a bus, the bus interface including a data buffer, the host system including a host driver, the method comprising:

interfacing the host system to the bus;

controlling and monitoring communication functionality between the data buffer and the bus including;

consolidating a summary of interrupt status information of interrupts arising from a plurality of functional blocks coupled to the bus;

posting the summary of interrupt status information in a storage that is readable by the host driver;

storing a mirror image of the summary of interrupt status information; and

automatically updating the mirror image when a change occurs in the summary of interrupt status information.

43. A method according to claim 42 further comprising:

accessing the summary of interrupt status information via a bus access operation;

changing the summary of interrupt status information; and

monitoring the result of the change in the summary of interrupt status information and in the mirror image without an additional bus read access.

44. A method according to claim 42 further comprising:

preposting an interrupt value in the mirror image before a bus interrupt signal is activated when an automatic interrupt posting status update functionality is enabled; and

activating the bus interrupt signal without delay when the automatic interrupt posting status update functionality is not enabled.

45. A method according to claim 42 further comprising:

transmitting data from the data buffer over the bus using a direct memory access (DMA) operation including a read and compare option so that interrupt status information is posted into a storage in the system memory that mirrors the interrupt posting status register and checks for any update during the direct memory access operation.

46. A method according to claim 42 further comprising:

handling dual interrupt requests including one interrupt request for normal interrupts and a second interrupt request for abnormal interrupts.

47. A method according to claim 46 further comprising:

programming interrupt requests for normal interrupts and for abnormal interrupts; and

merging the normal interrupt requests and abnormal interrupt requests into a single interrupt.

48. A method according to claim 46 further comprising:

queuing a plurality of command completions on a single interrupt.

49. A method according to claim 42 further comprising:

individually controlling issue of a plurality of interrupts.