Method and apparatus for distinguishing register reads from memory reads in a flash memory

• US 6,085,282 A
• Filed: 09/24/1997
• Issued: 07/04/2000
• Est. Priority Date: 09/24/1997
• Status: Expired due to Term

• Current Assignee: Progressive Semiconductor Solutions LLC (Acacia Research Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hansen, John Phillip, Metzger, Erik
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Portka, Gary J.
• Application Number:
  US08/936,371
• Time in Patent Office: 1,014 Days
• Field of Search: 711/103, 711/156, 711/170, 365/185.33, 365/189.01, 365/189.03, 365/189.04, 365/189.05, 365/189.07
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A non-volatile memory (12) such as FLASH provides for two modes of operation: command mode and memory mode. Read requests in command mode read non-volatile memory status information, such as from status registers (29). Reads in memory mode return data stored in a non-volatile memory array (20, 22). A command mode read is distinguished from a memory mode read by whether a command mode indication is received within the same memory cycle as a read indication. The command read indication may be an operand address within a prespecified range of memory addresses or through a dedicated input pin. The prespecified memory addresses may be memory-mapped to status registers (29), allowing reads of status registers (29) when an operand address is within the prespecified range without the necessity of entering and leaving command mode, and otherwise to data (20, 22) stored in the non-volatile memory (12).

Claims

1. A data processing system comprising:

a processor and

a non-volatile memory, and

an interface coupling the processor and the non-volatile memory comprising;

a plurality of data lines for providing a plurality of data signals, and

a first plurality of address lines for providing a plurality of address signals for specifying an operand address,

wherein;

a write command received from the processor for the non-volatile memory puts the non-volatile memory into a command mode;

a read command received from the processor for the non-volatile memory received along with a command read indicator within a same memory cycle indicates a command mode read of a control or status register for the non-volatile memory, and

the read command received from the processor for the non-volatile memory that is received without the command read indicator within the same memory cycle as the read command indicates a memory read of a plurality of bits from the non-volatile memory and transmission of the plurality of bits over the plurality of data lines to the processor, wherein the read command for a command mode read of the control or status register is distinguished from the read command for a memory read solely by the command read indicator, and the command read indicator is provided in addition to the read command.

2. The data processing system in claim 1 wherein:

the command read indicator is an input signal received by the non-volatile memory.

3. The data processing system in claim 2 wherein:

the input signal is derived from a one of a second plurality of address lines.

4. The data processing system in claim 1 wherein:

the interface further comprises;

a write enable line for providing a write enable signal, and

a chip enable line for providing a chip enable signal, and

a write request is indicated by assertion of the chip enable signal and assertion of the write enable signal.

5. The data processing system in claim 1 wherein:

the interface further comprises;

a write enable line for providing a write enable signal, and

a chip enable line for providing a chip enable signal, wherein a read request is indicated by assertion of the chip enable signal and a negation of the write enable signal.

6. The data processing system in claim 1 wherein:

the non-volatile memory is flash memory.

7. A non-volatile memory comprising:

a memory array;

a control circuit for controlling read functions to and command functions for the memory array;

an interface comprising;

a first plurality of address terminals for receiving a plurality of address signals that specify an operand address, and

a plurality of data terminals for receiving and transmitting a plurality of data signals; and

wherein;

a write command received by the non-volatile memory puts the non-volatile memory into a command mode,

a read command received within a same memory cycle as a command read indicator is received indicates a command mode read of a control or status register for the non-volatile memory, and

the read command received without the command read indicator within the same memory cycle as the read command is received indicates a read of a plurality of data bits from the memory array and transmission of the plurality of data bits as the plurality of data signals wherein the read command for a command mode read of the control or status register is distinguished from the read command for a memory read solely by the command read indicator, and the command read indicator is provided in addition to the read command.

8. The non-volatile memory in claim 7 wherein:

the command read indicator is an input signal received by the non-volatile memory.

9. The non-volatile memory in claim 8 wherein:

the input signal is derived from a one of a second plurality of address lines.

10. The non-volatile memory in claim 7 wherein:

the interface further comprises;

a write enable line for providing a write enable signal, and

a chip enable line for providing a chip enable signal, and

a write request is indicated by assertion of the chip enable signal and assertion of the write enable signal.

11. The non-volatile memory in claim 7 wherein:

the interface further comprises;

a write enable line for providing a write enable signal, and

a chip enable line for providing a chip enable signal, and

a read request is indicated by assertion of the chip enable signal and a negation of the write enable signal.

12. The non-volatile memory in claim 7 wherein:

the non-volatile memory is flash memory.