Method of operating a memory device having a variable data output length and an identification register

• US 6,085,284 A
• Filed: 02/19/1999
• Issued: 07/04/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/252,993
• Time in Patent Office: 501 Days
• Field of Search: 713/400, 713/600, 710/3-5, 710/9-12, 710/36-37, 710/51, 710/61, 710/129-137, 710/100-105, 710/167-169, 365/189.01-189.08, 365/230.01-230.06, 365/233
• US Class Current: 711/105
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of operating a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus. Block size information is provided to the memory device, wherein the block size information specifies an amount of data to be output onto a bus in response to a read request. The read request is issued to the memory device, and includes identification information, wherein in response to the read request, the memory device determines whether the identification information corresponds to the identification value stored in the register. When the identification information corresponds to the identification value, the memory device outputs an amount of data corresponding to the block size information onto the bus synchronously with respect to at least a first external clock. The memory device may further include a programmable register. An access time value may be provided to the memory device wherein, in response, the memory device stores the access time value in the programmable register. Here, the access time value is representative of a delay to transpire before data is output onto the bus in response to the read request.

Claims

1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus, the method of controlling the memory device comprises:

providing block size information to the memory device, wherein the block size information specifies an amount of data to be output by the memory device onto the bus in response to a read request; and

issuing the read request to the memory device which includes identification information, wherein in response to the read request, the memory device determines whether the identification information corresponds to the identification value stored in the register and when the identification information corresponds to the identification value, the memory device outputs the amount of data corresponding to the block size information onto the bus synchronously with respect to at least a first external clock.

2. The method of claim 1 wherein the read request and the block size information are contained in a transaction request packet.

3. The method of claim 2 wherein the read request and the block size information are contained in the same transaction request packet.

4. The method of claim 1 wherein the block size information further defines an amount of data to be input by the memory device from the bus in response to a write request, the method further including issuing a write request to the memory device which includes identification information, wherein in response to the write request, the memory device determines whether the identification information corresponds to the identification value stored in the register and when the identification information corresponds to the identification value, the memory device inputs the amount of data corresponding to the block size information synchronously with respect to at least the first external clock.

5. The method of claim 4 wherein the write request and the block size information are contained in a transaction request packet.

6. The method of claim 5 wherein the write request and the block size information are contained in the same transaction request packet.

7. The method of claim 1 wherein the memory device further includes a programmable register, and the method further includes.

providing an access time value to the memory device wherein, in response, the memory device stores the access time value in the programmable register, the access time value being representative of a delay to transpire before data is output onto the bus in response to the read request, and

wherein the amount of data corresponding to the block size information is output in accordance with the access time value during a plurality of cycles of the at least the first external clock.

8. The method of claim 7 wherein the access time value represents a fraction or an integer multiple number of cycles of the first external clock.

9. The method of claim 1 wherein the amount of data corresponding to the block size information is output synchronously with respect to the first external clock and a second external clock during a plurality of clock cycles of the first and second external clocks wherein the first and second clocks have a substantially fixed frequency.

10. The method of claim 9 further including generating at least one internal clock signal using a delay locked loop and the first external clock wherein the amount of data corresponding to the block size information is output onto the bus synchronously with respect to at least one internal clock signal.

11. The method of claim 10 wherein the delay locked loop generates the first internal clock using the first and the second external clocks.

12. The method of claim 1 wherein the register stores a unique identification value to identify the memory device from a plurality of other memory devices on the bus.

13. The method of claim 1 further including issuing the identification value which identifies the memory device on the bus to the register when the memory device is initialized.

14. The memory device of claim 1 wherein the register stores a device identification value to identify the memory device and a plurality of other memory devices on the bus.

15. The memory device of claim 1 wherein the block size information is a binary code indicative of the amount of data to be output in response to the read request.

30. The method of claim 6 further including receiving the identification value during an initialization sequence.

16. A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus, the method of operation of the memory device comprises:

receiving block size information from a master, wherein the block size information specifies an amount of data to be output by the memory device onto the bus in response to a read request or a write request;

receiving the read request from the master which includes identification information;

determining whether the identification information corresponds to the identification value stored in the register; and

outputting the amount of data corresponding to the block size information, in response to the read request, onto the bus synchronously with respect to at least a first external clock when the identification information corresponds to the identification value.

17. The method of claim 16 wherein the read request and the block size information are contained in a transaction request packet.

18. The method of claim 16 wherein the read request and the block size information are contained in the same transaction request packet.

19. The method of claim 16 wherein block size information further defines an amount of data to be input by the memory device from the bus in response to a write request, the method further including:

receiving a write request, which includes identification information, from the master;

determining whether the identification information in the write request corresponds to the identification value stored in the register; and

inputting the amount of data corresponding to the block size information, in response to the write request, from the bus synchronously with respect to at least a first external clock when the identification information corresponds to the identification value.

20. The method of claim 19 wherein the write request and the block size information are contained in the same transaction request packet.

21. The method of claim 16 further including storing an access time value in an access time register, the access time value being representative of a delay to transpire before data is output onto the bus in response to the read request.

22. The method of claim 21 wherein the access time value represents a fraction or a whole number of cycles of the first external clock.

23. The method of claim 21 wherein the amount of data corresponding to the block size information is output in accordance to the access time value over a plurality of cycles of the at least the first external clock.

24. The method of claim 21 wherein the access time value stored in the access time register is defined by a hard wired value.

25. The method of claim 16 further including outputting the amount of data corresponding to the block size information synchronously with respect to the first external clock and a second external clock wherein the data is output over a plurality of clock cycles of the first and second external clocks.

26. The method of claim 16 further including generating a first internal clock using a first delay locked loop wherein, in response to the first internal clock signal, the memory device outputs data.

27. The method of claim 26 wherein the first delay locked loop generates the first internal clock using the first and the second external clocks.

28. The method of claim 16 further including generating a first internal clock using a first delay locked loop and generating a second internal clock using a second delay locked loop wherein, in response to the first and second internal clock signals, the memory device outputs data.

29. The method of claim 16 further including:

receiving an identification value which identifies the memory device from a plurality of other memory devices on the bus; and

storing the identification value in the register.

31. The method of claim 16 further including:

receiving an identification value which identifies the memory device and a plurality of other memory devices on the bus; and

storing the identification value in the register.

32. The method of claim 16 wherein the block size information is a binary code.

33. A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells, an identification register to store an identification value which identifies the memory device on a bus, and an access time register to store an access time value which is representative of a delay to transpire before data is output onto the bus, the method comprises

storing the access time value in the access time register;

receiving block size information, wherein the block size information specifies an amount of data to be output in response to a read request or input in response to a write request;

receiving a read request which includes identification information;

determining whether the identification information in the read request corresponds to the identification value stored in the identification register;

outputting the amount of data corresponding to the block size information, in response to the read request, onto the bus synchronously with respect to at least a first external clock when the identification information in the read request corresponds to the identification value;

receiving a write request which includes identification information;

determining whether the identification information in the write request corresponds to the identification value stored in the identification register;

inputting the amount of data corresponding to the block size information, in response to the write request, from the bus synchronously with respect to the first external clock when the identification information in the write request corresponds to the identification value stored in the identification register.

34. The method of claim 33 wherein the read request and the block size information are contained in the same transaction request packet.

35. The method of claim 33 wherein the write request and the block size information are contained in the same transaction request packet.

36. The method of claim 33 wherein the access time value represents a fraction or whole number of cycles of the first external clock.

37. The method of claim 33 further including generating a first internal clock using a first delay locked loop and generating a second internal clock using a second delay locked loop wherein, in response to the first and second internal clock signals, an output driver outputs data onto the bus.

38. The method of claim 37 wherein the first delay locked loop generates the first internal clock using the first external clock and a second external clock.

39. The method of claim 33 further including generating an internal clock using a first delay locked loop wherein, in response to the first internal clock signals, an output driver outputs data onto the bus.

40. The method of claim 39 wherein the first delay locked loop generates the first internal clock using the first external clock and a second external clock.